Physical Design Engineer - Singapore

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip.

Responsibilities:

• Own the physical implementation of one or multiple critical blocks/subsystem/SOC from netlist to GDS, including early-stage feasibility analysis.
• Drive block/subystem/SOC PI/PV/timing signoff and ensure signoff closure.
• Push PPA (Power, Performance, Area) optimization for high-performance cores.
• Work closely with RTL, Synthesis, DFT, and STA teams to identify root causes and drive closure of complex implementation issues.

Requirements:

Minimum Qualification(s):

• BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 5+ years of experience in physical design / physical implementation.
• Experience owning complex digital block/subsystems/SOC from netlist to tapeout.
• Hands-on experience with industry-standard PD tools (e.g., Synopsys ICC2, Cadence Innovus).
• Experience with floorplanning, partitioning, and cross-block timing closure.

Preferred Qualification(s):

• Experience with 7nm/5nm/3nm/2nm or other advanced nodes.
• Experience owning complex block/subsystems/SOC such as AI core, or DDR/Ethernet PCS/PCIe/UCIe blocks, NOC/fabric; or CPU/GPU/NPU subsystems, NOC, memory controllers for server-level chips.