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RTL Design Engineer

Broadcom

RTL Design Engineer

Broadcom

2 Locations

·

On-site

·

Full-time

·

1w ago

Compensation

$127,100 - $203,400

Benefits & Perks

Healthcare

401(k)

Equity

Employee Stock Purchase Program

Employee Assistance Program

Paid Family Leave

Healthcare

401k

Equity

Required Skills

Verilog

SystemVerilog

RTL Design

Perl

Python

Tcl

Timing Analysis

Synthesis

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Job Description:

Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

  • Define the digital architecture and verification strategies for complex AMS and IO subsytems
  • Design, synthesis, and verification of Verilog/System Verilog RTL.
  • Analysis, debug, and resolution of Lint and CDC issues in the design.
  • Design convergence to timing closure utilizing RTL optimization strategies.
  • Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
  • Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
  • Drive comprehensive test plans to ensure quality of design.
  • Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
  • Create and maintain detailed specification, design, and verification documentation.

Job Requirements:

  • MS +10 years of relevant industry experience.
  • Experience with digital implementation flow from RTL synthesis to timing closure.
  • Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
  • Experience with Tessent tool for DFT insertion and verification
  • Proficient with Perl, Python and Tcl scripting.
  • Strong problem solving skills with attention to detail.
  • Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications:

  • Solid understanding of transistor-level circuit behavior.
  • Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
  • Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $127,100 - $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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About Broadcom

Broadcom

A designer, developer, and global supplier of a broad range of analog and digital semiconductor connectivity solutions.

10,001+

Employees

Palo Alto

Headquarters

Reviews

3.0

10 reviews

Work Life Balance

2.2

Compensation

4.1

Culture

2.3

Career

1.8

Management

2.1

25%

Recommend to a Friend

Pros

Good pay and compensation

Quality benefits package

Equity/RSUs offered

Cons

No career advancement opportunities

Poor management quality and leadership

Frequent layoffs and job insecurity

Salary Ranges

1,961 data points

Mid/L4

Mid/L4 · Infrastructure Engineer

1 reports

$219,086

total / year

Base

$168,682

Stock

-

Bonus

-

$219,086

$219,086

Interview Experience

2 interviews

Difficulty

3.0

/ 5

Duration

14-28 weeks

Experience

Positive 0%

Neutral 50%

Negative 50%

Interview Process

1

Interview

2

Multiple rounds