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Job Description:

Responsibilities include:

• Design analog blocks, systems or sub-systems using a combination of behavioral modeling tools and transistor-level circuit design tools.
• Must be capable of implementing and optimizing circuit architectures and transistor-level circuit solutions to achieve a variety of challenging performance, power consumption and cost requirements.
• Help take responsibility for projects with a team of analog and digital engineers.
• Draw or oversee the drawing of the custom physical layout of these circuits.
• Work with others to define circuit board components to be used with these circuits.
• Define requirements for internal chip interfaces between the analog and digital circuits.
• Review the chip package pinout/ballout and review and revise the chip package route with package layout engineers.
• Design and/or review the PC test board schematics used for testing the IC performance.
• Characterize the performance of these ICs using lab equipment.
• Debug performance problems found during characterization of these analog circuits.
• Work with automatic test engineers (ATE) to develop production tests for these circuits.
• Document the operation and performance of these analog circuits.
• The candidate will be responsible for the design of critical IPs such as opamps, comparators, bandgaps, ADCs, DACs, current sensors, temperature sensors, LDOs, rectifiers, buck converters, boost converters, buck-boost converters and battery chargers.
• The applicant could be an individual contributor or direct small design teams to facilitate the architecture definition, design, verification, and documentation of IC products.
• Simulation verification includes corner simulation, monte-carlo mismatch analysis, aging, and device over-voltage stress analysis for both pre and postlayout efforts.

Requirements:

• Proficiency in analog design and in-depth knowledge of CMOS devices.
• In-depth knowledge of analog and high-voltage layout techniques.
• Knowledge of switched power supplies, high-voltage BCD technologies and high-voltage/power circuitry is highly desirable.
• Intuitive understanding and ability to optimize circuit power, area, and performance.
• Skill running simulations, doing layout design and performing verification and extraction.
• Design environment/experience with CAD tools and thorough working knowledge of Cadence design tools.
• Transistor-level design (Cadence Analog artist).
• Layout tools (Cadence Virtuoso).
• Verification/extraction.
• Experimental verification/ATE support.
• Bench testing knowledge for post-silicon evaluation is a plus.
• Good communication skills.
• Able to work in a team environment.

Education and Experience:

• Bachelors and 12 years of related experience; or
• Masters degree and 10 years of related experience; or
• PhD and 7 years of related experience

Additional Job Description: Compensation and Benefits

The annual base salary range for this position is $127,100 - $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.