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Required Skills
Python
Excel
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Job Description:
This opening is for working on chips that enable Physical Layer Products for High
Speed Optical Communication.
architect block level design specifications from the marketing requirements and/or
system requirements
prepare detailed design document, timing constraint file
RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate level
simulations & silicon debug
Scripting for various IC design tasks such as STA, equivalency checks, test bench,
simulations, synthesis, etc.
prepare block level resource requirements & development schedule
generate verification & test plans for design validation
Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource,
priority, etc.
silicon bring up and validation, ATE program bring up
Job Requirement:
B.S degree in EE or computer Engineering. Minimum of 5 years of work experience with direct related technical skill
M.S degree/Ph.D in EE or Computer Engineering with 3 years of work experience.
Good knowledge of ARM subsystem
Good knowledge of high speed digital circuit design.
Good knowledge of digital upsampling/downsampling
Good knowledge of 10G/100G/200G/400G/800G Ethernet and OTN network.
Good knowledge on FEC (Forward Error Correction) design.
Good knowledge of digital signal processing and error correction code is a plus
Strong analytical and problem solving skills as well as hands-on lab debugging
experiences
Good knowledge of RTL simulation and synthesis.
In-depth knowledge for design for low power and design for test and design for
manufacturing.
Good Knowledge in languages relevant to the ASIC development process including
Verilog, VHDL, Unix/Perl Scripting or Python, and C.
Self-motivated, excellent communication skills and ability to excel in a team
environment.
Good organization skills, able to follow through & bring issue to closure
Understand the entire IC development flow & procedure including silicon volume
production qualification requirements & procedures
Enthusiastic & enjoy IC development works
Be able to work with teams at remote locations with different time zone.
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $91,000 - $146,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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About Broadcom
Reviews
3.0
10 reviews
Work Life Balance
2.2
Compensation
4.1
Culture
2.3
Career
1.8
Management
2.1
25%
Recommend to a Friend
Pros
Good pay and compensation
Quality benefits package
Equity/RSUs offered
Cons
No career advancement opportunities
Poor management quality and leadership
Frequent layoffs and job insecurity
Salary Ranges
1,961 data points
Mid/L4
Mid/L4 · Infrastructure Engineer
1 reports
$219,086
total / year
Base
$168,682
Stock
-
Bonus
-
$219,086
$219,086
Interview Experience
2 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Experience
Positive 0%
Neutral 50%
Negative 50%
Interview Process
1
Interview
2
Multiple rounds
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