Staff Verification Engineer:

We are seeking a highly skilled Verification Engineer to drive unit-level verification of complex digital IP blocks.

The ideal candidate will have deep expertise in System Verilog (SV), UVM methodology, and power-aware verification (UPF/CPF).

You will be responsible for ensuring design correctness, low-power compliance, and robust analog/digital interaction at the block and subsystem level.

Education and Experience:

• Bachelor's or Master's degree in Electronics or Electrical Engineering (or equivalent).

• 10-12 years of experience in block-level or unit-level functional verification with exposure to AMS and low-power design verification

• Develop UVM-based verification environments for digital IPs at the unit level.

• Create System Verilog testbenches, drivers, monitors, and scoreboards to validate functional and timing behavior.

• Define and execute power-aware verification plans using UPF/CPF, covering power gating, isolation, retention, and level-shifting behavior.

• Develop assertion-based verification (SVA) for functional and low-power checks.

• Build and maintain functional coverage models, track coverage closure, and identify verification gaps.

• Collaborate closely with design, analog, and SoC verification teams to align stimulus and interface models.

• Debug simulation issues using waveform analysis and low-power debugging tools.

• Provide technical guidance and methodology improvements for mixed-signal and low-power verification.

• Essential Skills

• Strong proficiency in System Verilog and UVM testbench architecture.

• Working knowledge of power-aware verification with UPF/CPF, including isolation, retention, and power-switch modeling.

• Hands-on experience with simulation and debug tools (Synopsys VCS, Cadence Xcelium, Siemens Questa).

• Exposure to low-power design techniques (clock gating, power domains, voltage scaling).

• Knowledge of SVA and functional coverage methodology.

• Preferred Skills

• Understanding of analog front-end circuits (e.g., PLLs, ADCs, PMICs, LDOs, sensor interfaces).

• Experience in formal verification or assertion-based formal checks for power and control logic.

• Integrate AMS co-simulation (e.g., Cadence Xcelium AMS, Synopsys VCS AMS) and ensure convergence across analog and digital domains.

• Experience with Analog-Mixed-Signal verification using Verilog-AMS or real-number modeling (RNM).

• Scripting and automation skills in Python, Perl, or Shell.

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm:

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.