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SoC Design Integration Engineer

Apple

SoC Design Integration Engineer

Apple

Irvine, CA

·

On-site

·

Full-time

·

2d ago

We're looking for individuals who relish a good challenge and are dedicated to overcoming limits. You'll be at the heart of chip design! Apple recently announced first in-house cellular modem platforms, the C1 and C1X, designed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple's custom silicon. You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you'll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product?

As a member of Cellular SoC design team, you will be at the center of a SoC design and integration at the leading process technology node with a critical impact on getting functional products to millions of customers. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.

Description

As a SoC Integration Engineer, you will have responsibilities to design and integrate IPs.

  • Working with other specialists that are members of the SoC Design, SoC Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows for sophisticated So Cs.

  • Integrating various IPs and ensuring design meets DFT (design-for-test), CDC (clock domain crossing), Synthesis/Static Timing and Power Requirements.

  • Developing micro-architecture and design specifications.

  • Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability and improve front-end design methodologies.

  • Implementing and verifying sophisticated logic designs.

  • Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases; from concept to silicon bring-up.","responsibilities":"IP Integration: Integrate third-party or internal IP blocks (e.g., CPU, memory controllers, custom logic, Mixed Signal/Analog IOs) into a SoC.

RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are correctly implemented.

Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects.

Explore the use of AI/ML tools to improve SoC Design and Integration.

Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality.

Timing Closure: Work closely with physical design and STA teams to achieve timing closure at top level.

Functional Verification Support: Provide integration-level support to design verification teams, including simulation bring-up and debug.

Documentation and Reviews: Create and maintain design documents and participate in design reviews.

Preferred Qualifications

Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence).

Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR, SPI, SPMI, I2C, I3C, etc.).

Decent scripting skills (Python, Perl, TCL, Shell) for automation.

Good debugging and problem-solving skills.

Excellent communication and cross-functional collaboration.

Minimum Qualifications

BS and 10+ years of relevant industry experience.

Solid understanding of digital logic design and RTL development (System Verilog, Verilog).

Knowledge of low-power design techniques and power optimization strategies.

Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.

Knowledge of ASIC tool flows: lint, synthesis, CDC, RDC, DFT, STA.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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Appleについて

Apple

Apple

Public

Apple Inc. is an American multinational technology company headquartered in Cupertino, California, in Silicon Valley, best known for its consumer electronics, software and online services.

10,001+

従業員数

Cupertino

本社所在地

$3.5T

企業価値

レビュー

3.9

10件のレビュー

ワークライフバランス

2.5

報酬

4.2

企業文化

3.8

キャリア

3.5

経営陣

3.2

72%

友人に勧める

良い点

Great benefits and compensation

Talented colleagues and supportive teams

Learning opportunities and mentorship

改善点

Work-life balance challenges

High stress and pressure

Fast-paced environment

給与レンジ

11,365件のデータ

L2

L3

L4

L5

L6

L2 · Business Analyst L2

0件のレポート

$114,215

年収総額

基本給

$45,686

ストック

$57,108

ボーナス

$11,422

$79,951

$148,480

面接体験

3件の面接

難易度

3.3

/ 5

期間

28-42週間

内定率

33%

体験

ポジティブ 33%

普通 0%

ネガティブ 67%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

よくある質問

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Past Experience