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Do you have a passion for invention and self-challenge. Do you thrive with pushing the limits of what's considered feasible? As part of an outstanding team, you'll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You'll work across fields to transform improved hardware elements into a coordinated design. Join us, and you'll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you'll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide.
Description
The wireless RFIC team architects, designs, and validates radio transceivers integrated into sophisticated wireless So Cs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by an outstanding vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering! As an engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group, chipping in to Apple's innovative wireless connectivity solutions into hundreds of millions of products.","responsibilities":"As an RFIC Design Engineer, you will be responsible for providing RFIC solutions for wireless SoC and driving them to mass production for Apple's Wireless Connectivity products. Responsibilities include:
Led design of radio transceiver chains, including TX, RX, and PLL-LOGen for wireless connectivity products.
Drive radio KPI (power, area, performance) to meet product requirements.
Work with multi-functional teams including platform architecture, wireless design, RF HW and SW to define radio features enabling wireless innovation.
Work closely with RF Systems in block level and high level specifications of the TX and RX line ups and PLL-LOGen, and accurate distribution of spec margins in the chain.
Hands-on design contributions, starting from concept, architecture, and topology to transistor-level feasibility studies and KPI trade-off analysis to actual design, simulations, and extractions.
Design of RF and Analog loopbacks for calibration and compensation.
Work through Co-Existence scenarios and design to meet the Co Ex requirements.
Be responsible for the floorplan layout and verification of the design to ensure a successful tape-out.
Close collaboration with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization.
Provide design versus silicon measurements correlation and compliance with specifications for volume production.
Preferred Qualifications
MSEE and PhD plus relevant industry experience.
Solid Understanding of the impact of modulation type on radio architecture and requirements.
Validated capability to work with digital design group for an optimum partition between digital and analog domains.
Familiarity with the integration flows and challenges of wireless SoC's.
Good understanding of desense and can work with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation.
Familiarity with mixed-signal mode verification methodology (System Verilog, AMS, Nanotime).
Extensive experience in Silicon characterization and debugging.
Ability to drive strong production test/QA methodologies.
Minimum Qualifications
BS and 10+ years of relevant industry experience.
Shown RF/analog and mixed-signal design experience in groundbreaking RF CMOS design.
Strong understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
Experience in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.
Direct experience in designing and bringing wireless transceivers into mass production in deep sub-micron RFCMOS technology.
Experience should also include understanding DFT and DFM techniques for mass production environments.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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Appleについて

Apple
PublicApple Inc. is an American multinational technology company headquartered in Cupertino, California, in Silicon Valley, best known for its consumer electronics, software and online services.
10,001+
従業員数
Cupertino
本社所在地
$3.5T
企業価値
レビュー
3.9
10件のレビュー
ワークライフバランス
2.5
報酬
4.2
企業文化
3.8
キャリア
3.5
経営陣
3.2
72%
友人に勧める
良い点
Great benefits and compensation
Talented colleagues and supportive teams
Learning opportunities and mentorship
改善点
Work-life balance challenges
High stress and pressure
Fast-paced environment
給与レンジ
11,365件のデータ
L2
L3
L4
L5
L6
L2 · Business Analyst L2
0件のレポート
$114,215
年収総額
基本給
$45,686
ストック
$57,108
ボーナス
$11,422
$79,951
$148,480
面接体験
3件の面接
難易度
3.3
/ 5
期間
28-42週間
内定率
33%
体験
ポジティブ 33%
普通 0%
ネガティブ 67%
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
よくある質問
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Past Experience
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