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Description:

APPLE INC has the following available in Austin, Texas. Responsible for physical design and implementation of partitions. Work with logic design team to understand partition architecture and drive physical aspects early in design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and designing goals. Conduct timing, physical & electrical verification. Drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identifying potential solutions, and driving execution. Modify and run caliber based runsets for DRC, Antenna and ERC checking. Load layout with caliber DRV to review verification results and provide feedback to physical design peers. Develop handoff timelines and quality metrics geared towards successful milestone completion throughout project design cycle. Maintain knowledge of latest foundry manufacturing design rule manuals for each relevant technology node. 40 hours/week.

Preferred Qualifications:

N/A

Minimum Qualifications:

Bachelor's degree or foreign equivalent in Electrical Engineering or a related field.

Experience and/or education must include:

Using physical verification, including DRC and LVS flows to enable custom runset design as needed.

Using GDSII layout vs Spice schematic verification for ensuring manufacturability of designs delivered to foundry.

Using Perl, TCL and shell scripting for task automation.

Troubleshooting integration process and PV flow related design issues to facilitate block design closure.

Using physical design for ASIC/FPGA methodology to understand physical design workflows.

Using device physics including device and transistor levels to help maintain understanding of latest process technologies.

Utilizing CAD tools including Cadence Virtuoso, Spice, Calibre design Rev for reviewing layout and schematics to enable violation review.

Using Place and Route tools including IC Compiler or EDI for running the PNR flow and assisting designers with PNR review.

Utilizing ESD and High Voltage implementation and physical verification methodology to drive ESD planning in early project design phases and work with teams to ensure DRC and PERCESD clean implementations.

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