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We are seeking an ASIC Power Engineer to drive SoC power simulation, analysis and optimization for next-generation wireless SOC products. This role requires deep technical expertise in power estimation and a passion for developing highly power-efficient So Cs that enable breakthrough wireless experience.
Description
In this highly visible role, you will be responsible for SoC power estimation, use case power analysis, and driving future SoC power optimization strategies. You will work with a team of talented engineers to integrate innovative power solutions and deliver industry-leading power efficiency.
The position focuses on SoC power estimation and optimization for power-critical wireless products.
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Work with architects to define power-critical use cases and scenarios.
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Establish power targets and collaborate with cross-functional teams to achieve optimization goals.
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Define comprehensive test cases within design verification environments.
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Generate accurate pre-silicon power estimations for design decision-making.
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Analyze power consumption patterns and identify optimization opportunities.
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Develop SoC power models for new architecture designs, enabling performance/power trade-off analysis.
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Understand software and system-level interactions that impact overall power consumption.
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Partner with lab and silicon characterization teams to correlate models with measured silicon data.","responsibilities":"Perform comprehensive SoC power simulation and analysis using Pt Px and PPRTL tools across multiple wireless use cases and operating scenarios.
Develop and maintain accurate power models for new wireless SoC architectures, enabling early power-performance trade-off analysis during design phases.
Collaborate with silicon design teams, architects, and verification engineers to define power-critical test scenarios and establish realistic power targets for wireless connectivity features.
Drive pre-silicon power estimation and post-silicon correlation activities, working closely with Silicon validation teams to validate and refine power models against measured silicon data.
Identify and quantify power optimization opportunities across architecture, RTL, and physical implementation levels, providing actionable recommendations to design teams.
Analyze system-level power interactions between wireless subsystems and other SoC components to optimize overall power efficiency.
Create and maintain automated power analysis flows and methodologies to support multiple concurrent SoC development programs.
Present power analysis results and optimization strategies to cross-functional teams and senior leadership.
Preferred Qualifications
Understanding of electrical properties of on-die PDN, power gating, package and system power delivery.
Hands-on experience with SoC power domains and power management unit (PMU) interactions in complex multi-core chipsets.
Knowledge of power impact at architecture, logic design, and circuit levels.
Experience in power model development for complex So Cs.
Familiarity with SoC design flow and methodology.
Strong communication skills to collaborate effectively across multiple engineering disciplines.
Knowledge of Wi Fi or Bluetooth standards and protocols.
Minimum Qualifications
BS in Electrical Engineering, Computer Engineering, or related technical field and 10+ years of relevant industry experience.
Hands-on experience with Pt Px and PPRTL power analysis tools.
Experience in SoC power simulation, modeling, and analysis flow development.
Experience in ASIC power estimation, analysis and optimization methodologies.
Experience in power model development for IPs.
Hands-on experience in correlating pre-silicon power models with measured silicon data and driving model accuracy improvements through systematic debugging.
Proficiency in scripting languages including Python, Perl, or TCL.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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Appleについて

Apple
PublicApple Inc. is an American multinational technology company headquartered in Cupertino, California, in Silicon Valley, best known for its consumer electronics, software and online services.
10,001+
従業員数
Cupertino
本社所在地
$3.5T
企業価値
レビュー
3.9
10件のレビュー
ワークライフバランス
2.5
報酬
4.2
企業文化
3.8
キャリア
3.5
経営陣
3.2
72%
友人に勧める
良い点
Great benefits and compensation
Talented colleagues and supportive teams
Learning opportunities and mentorship
改善点
Work-life balance challenges
High stress and pressure
Fast-paced environment
給与レンジ
11,365件のデータ
L2
L3
L4
L5
L6
L2 · Business Analyst L2
0件のレポート
$114,215
年収総額
基本給
$45,686
ストック
$57,108
ボーナス
$11,422
$79,951
$148,480
面接体験
3件の面接
難易度
3.3
/ 5
期間
28-42週間
内定率
33%
体験
ポジティブ 33%
普通 0%
ネガティブ 67%
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
よくある質問
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Past Experience
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