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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Develop design for large SOC blocks including Internal and external IP integration and design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure. Ownership of the Integration Spec for the design project including integration and optimization of any memories and hard macros required for the block. Run synthesis, netlist generation, and timing closure for the block. Work closely with the owners of a test-bench generation flow to improve and maintain the flow. Read design specs, test plans, and design codes. Write tests and generate required files for DFT design verification. Run simulations and debug by checking logs, reports, designs and test files. Work with design team to solve the problems found in the simulations. Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs. Generate, verify, and release test patterns. Develop and implement DFT architecture. Work with the validation team to verify DFT implementations and implement design changes. Generate structural test vectors, analyzing and improving coverage. Work with designers on STA, physical, power and logical issues. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,471 - $213,700/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Preferred Qualifications

N/A

Minimum Qualifications

Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.

Experience and/or education must include:

Using Verilog, System Verilog, or VHDL to write RTL.

Running RTL simulations using industry standard tools like VCS, Modelsim, Sim Vision, or NCSIM to debug and fix the designs.

Using Static timing analysis (STA) to understand and implement DFT timing.

Using fault models, Scan test knowledge to implement DFT design and Automatic Test Pattern Generation (ATPG).

Utilizing JTAG architecture for DFT register planning and programming.

Automating DFT designs flows using Python or Perl.

Utilizing BIST architecture for DFT insertion and debugging the failures.

Using memory fault models to plan memory test architectures.

Utilizing clock domain crossing (CDC) to debug the CDC failures using industry stand tools from Cadence and Synopsys.

Utilizing low power design to reduce the overall chip power.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .