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Description

APPLE INC has the following available in Austin, Texas. Lead physical verification activities from early design stages through tape-out, working with front-end teams to set up verification requirements and methodologies. Run full-chip verification flows like DRC, LVS, antenna checking, and ERC across different design levels. Create floor planning guidelines that merge foundry rules with our chip requirements, debug verification issues with SoC and IP teams, and build standardized verification flows to help ensure working silicon on the first pass. Own the complete physical implementation for multiple design blocks. Handle everything from floor planning and cell placement to clock tree synthesis and routing. Create optimized floorplans with proper pin assignments and power networks, work with timing teams on constraints, and drive area and power optimizations to hit target specs. Handle final sign-off verification including timing analysis, electrical checks, and fixing any timing or signal integrity problems that come up during tape-out. Build and maintain automation tools using TCL, Python, Perl, and shell scripting to make physical design workflows more efficient. Write scripts that parse various file formats and EDA tool logs to automate analysis and reporting. Manage code using Git or Perforce, coordinate projects through tools like JIRA, and develop frameworks that integrate with standard EDA tools from Cadence, Synopsys, and Mentor Graphics. 40 hours/week.

Preferred Qualifications

N/A

Minimum Qualifications

Master's degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, Software Engineering, or related field and 3 years of experience in the job offered or related occupation.

2 years of experience with each of the following skills is required:

Experience with physical verification checks including design rule checks (DRC), layout vs schematic (LVS), antenna checks (ANT), and electrical rule checks (ERC) at partition, cluster and top design levels.

Provide project wide partition and top-level floor planning guidelines that integrate foundry requirements and design-specific PNR specifications.

Collaboration with SoC, IP top-level and partition teams by actively debugging, monitoring, and validating PDV adherence to achieve design convergence.

Using TCL, Python, Perl, Shell programming to design, develop, debug, and release automation tools.

Parsing and processing data formats including XML, JSON, CSV, or log files using regular expressions and specialized libraries for automated analysis of test results and hardware validation data.

Using project management and issue tracking tools including JIRA, Bugzilla, or similar platforms to track project timelines, collaborate, and assign tasks.

Proficiency in version control systems including Git, Perforce, or SVN with experience in multi-developer automation projects.

Utilizing knowledge in digital design fundamentals including comprehensive understanding of digital logic design principles, combinational and sequential circuit design, finite state machines, timing analysis concepts, and low power design.

Utilizing knowledge of underlying physical implementation including silicon processes, transistor characteristics, interconnect modeling, and wire delay effects.

Experience and/or Education must include:

Implementing multiple place and route (PNR) blocks through all design stages and tape-out (TO) closure process including floor planning, clock distribution (CTS), power distribution (PG), timing closure (STA), formal equivalence (LEQ), physical verification (PDV) and electrical verification (EMIR) using industry-standard tools including Cadence, Synopsys, or Mentor Graphics.

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