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RFIC - PLL Design Engineer

Apple

RFIC - PLL Design Engineer

Apple

Irvine, CA

·

On-site

·

Full-time

·

1d ago

Would you like to join Apple's growing wireless silicon development team? The wireless RFIC team architects, designs, and validates radio transceivers integrated into complex wireless So Cs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless connectivity solutions into hundreds of millions of products.

Description

As a RFIC-PLL Designer, you are going to contribute to providing analog and digital PLL solutions for wireless SoC and driving them to mass production for Apple's Wireless Connectivity products.","responsibilities":"Design and develop analog and digital PLL building blocks: VCO, DCO, MMD, PFD, Filter, TDC and so on.

Design and develop analog and digital PLL top levels.

Design and develop LOGEN building blocks and top level.

Work with cross-functional teams including platform architecture, wireless design, RF HW and SW to define radio features enabling wireless innovation.

Work closely with RF Systems in block level and top-level specifications of the PLL, LOGEN, as well as TX and RX line ups, and proper distribution of spec margins in the chain.

Contribute to feasibility studies and trade-off analysis

Contribute to design starting from concept, architecture and topology to actual transistor-level design and verification

Work through Co-Existence scenarios and design to meet requirements.

Oversee layout, floor planning and verification of the design toward a successful tape-out.

Collaborate closely with RFIC test engineers in the bring up, debug and optimization of the chip throughout the productization.

Provide design versus silicon measurements correlation, and compliance with specification for a volume production.

Preferred Qualifications

Ph.D. degree

Hands on experience in modeling, analysis and design of noise/spur cancellation techniques in PLLs.

Familiarity with various RF transceiver architectures and their trade-offs, system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level.

Familiarity with timing analysis tools (Nanotime, Primetime).

Direct experience in designing and bringing into mass production of wireless transceivers in deep sub-micron RFCMOS technology.

Demonstrated capability to work with digital design group for an optimum partition between digital and analog and contribute to providing comprehensive timing requirements.

Minimum Qualifications

BS and 10 + years of relevant industry experience.

Experienced in design and development of Analog and Digital PLLs and LOGEN for high performance applications.

Hands on experience in designing PLL building blocks: TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs and PFD/CP.

Deep understanding of analog, mixed-signal and RF circuit design concepts. This includes LNAs, PAs, mixers, baseband filters, VGAs and calibration methods associated with high performance wireless systems.

Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.

Familiarity with mixed-signal mode verification methodology (System Verilog, AMS).

Extensive experience in PLL and LOGEN silicon characterization and debug.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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关于Apple

Apple

Apple

Public

Apple Inc. is an American multinational technology company headquartered in Cupertino, California, in Silicon Valley, best known for its consumer electronics, software and online services.

10,001+

员工数

Cupertino

总部位置

$3.5T

企业估值

评价

3.9

10条评价

工作生活平衡

2.5

薪酬

4.2

企业文化

3.8

职业发展

3.5

管理层

3.2

72%

推荐给朋友

优点

Great benefits and compensation

Talented colleagues and supportive teams

Learning opportunities and mentorship

缺点

Work-life balance challenges

High stress and pressure

Fast-paced environment

薪资范围

11,365个数据点

L2

L3

L4

L5

L6

L2 · Business Analyst L2

0份报告

$114,215

年薪总额

基本工资

$45,686

股票

$57,108

奖金

$11,422

$79,951

$148,480

面试经验

3次面试

难度

3.3

/ 5

时长

28-42周

录用率

33%

体验

正面 33%

中性 0%

负面 67%

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

常见问题

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Past Experience