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Gate-level SigEM/SEB/FIT CAD Engineer

Apple

Gate-level SigEM/SEB/FIT CAD Engineer

Apple

Austin, TX

·

On-site

·

Full-time

·

1w ago

Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!

As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, SOC FIT budget validation, power-grid EM verification, 3DIC and interposer thermal integrity, power switch and standard cell EM/SHE characterization, design abstract and reuse, sign-off, and ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?

Description

In this highly visible role, your primary responsibilities will include:

  • Contribute to the development and deployment of comprehensive EM/SEB/thermal methodologies across multiple advanced node designs

  • Develop and implement customized EM/SEB/thermal solutions which scale with accuracy and capacity challenges, following established best practices and design guidelines

  • Support and maintain the EM/SEB/thermal flow from concept through sign-off, including automation, quality metrics, and continuous improvement

  • Collaborate with and support various teams (Physical design and Integration, Clock and Signal integrity, Circuit design, Power, Package, System, Technology) on EM/FIT requirements and trade-offs

  • Develop, validate, and maintain EM/thermal rule decks and verification methodologies for clock trees, high-speed data paths, and critical signal nets across multiple projects

  • Work closely with EDA vendors and foundries for tool qualification, model development, enhancement requests, and roadmap alignment

  • Participate in correlation studies between EM analysis tools and silicon failure analysis data, contributing to methodology improvements based on findings

Preferred Qualifications

Understanding of current density calculations, heating effects, and electromigration failure mechanisms

Experience in some of the analysis involved in EM - extraction, timing, simulation, EM modeling, physical design, and physical verification

Experience in EDA tools and CAD flow development

Proficiency in at least one of Tcl, Python, or Perl scripting languages

Exposure to or knowledge of industry leading EMIR tools e.g. Voltus, Voltus-Fi, Red Hawk-SC, Totem

Experience with analysis, optimization, or debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon

Familiarity with advanced packaging technologies (2.5D/3D/3.5DIC) and their unique EM challenges

Interest in AI/ML-driven innovation for CAD workflows

Experience in development of software in multi-user, multi-site environments

Ability to coordinate and drive initiatives with appropriate guidance

Strong communication and presentation skills

Minimum Qualifications

Experience with EM/SEB/FIT/SHE/Thermal methodologies and calculations

Minimum BS + 3 years of relevant industry experience

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Pay & Benefits

Apple accepts applications to this posting on an ongoing basis.

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  • US"},"posting Date":"2026-02-25T20:52:17.606+00:00"},"post Location-SFMETRO":{"posting Supplement Footer":{"display Order":1,"content":"At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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Appleについて

Apple

Apple

Public

Apple Inc. is an American multinational technology company headquartered in Cupertino, California, in Silicon Valley, best known for its consumer electronics, software and online services.

10,001+

従業員数

Cupertino

本社所在地

$3.5T

企業価値

レビュー

3.9

10件のレビュー

ワークライフバランス

2.5

報酬

4.2

企業文化

3.8

キャリア

3.5

経営陣

3.2

72%

友人に勧める

良い点

Great benefits and compensation

Talented colleagues and supportive teams

Learning opportunities and mentorship

改善点

Work-life balance challenges

High stress and pressure

Fast-paced environment

給与レンジ

11,365件のデータ

L2

L3

L4

L5

L6

L2 · Business Analyst L2

0件のレポート

$114,215

年収総額

基本給

$45,686

ストック

$57,108

ボーナス

$11,422

$79,951

$148,480

面接体験

3件の面接

難易度

3.3

/ 5

期間

28-42週間

内定率

33%

体験

ポジティブ 33%

普通 0%

ネガティブ 67%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

よくある質問

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Past Experience