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SerDes Circuit Design Engineer

Apple

SerDes Circuit Design Engineer

Apple

San Diego, CA

·

On-site

·

Full-time

·

2d ago

We are seeking talented Analog Mixed-Signal designers to join our high-speed Ser Des team. Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple's world-leading system-on-chip (SOC).

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create, execute and drivestate-of-the-art IPs key to Apple's products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.

If you have strong fundamentals and a track record of tackling technical challenges,

If you are passionate about learning new skills and improving the value of your work,

If you like to be tuned to the big picture while diving deeply into the details to innovate and tackle problems.

We invite you to join and grow with our team!

Description

You will work on the development of high-performance and high-speed AMS circuits used in Ser Des PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best-in-class power, performance, and area (PPA).

You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.

Preferred Qualifications

Deep understanding of analog mixed-signal design with experience in high-speed serial links.

Experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters

Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques

Understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)

Proven track record of working with system and architecture teams to drive block-level and IP requirements for high-speed IO in 100+ Gbps NRZ and PAM applications

Proven track record of working with large teams and guiding junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO.

Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts

Experience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 100+ Gbps NRZ and PAM applications

Experience with EQ adaptation methods and circuit implementations to improve PPA

Solid understanding of CDR architectures and implementations

Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. System Verilog, Matlab, Python, VerilogAMS)

Hands-on experience to drive lab testing, debug and data analysis

Hands-on experience in advanced CMOS technologies, design with Fin Fet technology

Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization

Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)

Concepts of IP delivery and quality checks

Knowledge of common high-speed Ser Des protocols (e.g., PCIe, USB, DP, MPHY) is highly desired

Skills in scripting and automation to enhance efficiency are highly desirable

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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Appleについて

Apple

Apple

Public

Apple Inc. is an American multinational technology company headquartered in Cupertino, California, in Silicon Valley, best known for its consumer electronics, software and online services.

10,001+

従業員数

Cupertino

本社所在地

$3.5T

企業価値

レビュー

3.9

10件のレビュー

ワークライフバランス

2.5

報酬

4.2

企業文化

3.8

キャリア

3.5

経営陣

3.2

72%

友人に勧める

良い点

Great benefits and compensation

Talented colleagues and supportive teams

Learning opportunities and mentorship

改善点

Work-life balance challenges

High stress and pressure

Fast-paced environment

給与レンジ

11,365件のデータ

L2

L3

L4

L5

L6

L2 · Business Analyst L2

0件のレポート

$114,215

年収総額

基本給

$45,686

ストック

$57,108

ボーナス

$11,422

$79,951

$148,480

面接体験

3件の面接

難易度

3.3

/ 5

期間

28-42週間

内定率

33%

体験

ポジティブ 33%

普通 0%

ネガティブ 67%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Team Matching

6

Offer

よくある質問

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Past Experience