Formal Verification Engineer

Formal Verification Engineer

Summary

Ready for an intellectual challenge that combines Mathematics and CS theory in the context of hardware development? Keep reading.

In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence

Not in the Formal domain? No worries, we offer thorough training to learn the theory and practice directly from our team experts

Description

In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence .
The position is relevant for both Herzliya/ Haifa site

Minimum Qualifications

Excellent graduates from leading universities
Analytical thinking
Highly motivated

Preferred Qualifications

BS.c / MS.c in CS & Mathematics

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