
Together we advance.
Silicon Design Engineering Manager
報酬
CA$148,720 - CA$223,080
福利厚生
•育児休暇
•健康保険
必須スキル
DFT
RTL Design
Verilog
WHAT YOU DO AT AMD CHANGES EVERYTHING:
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.THE ROLE:
AMD seeks a passionate, collaborative leader with strong technical skills in the area of Design-for-Test (DFT) and the initiative to motivate an expert design team. The successful candidate will lead a high performance central DFT design team to develop advanced DFT features, tools and flows for high performance, adaptive compute products for AI data center, emdedded, gaming and PC markets.
THE PERSON: The ideal candidate has experience leading DFT design projects from project definition to design bring-up. You will establish a collaborative environment that fosters design innovation, verification know-hows and execution best practices. You can lead others in technical and managerial settings, which include mentoring and providing technical guidance. You also have excellent communication, writing, and presentation skills.
- KEY RESPONSIBILITIES:
Team Leadership & Management:
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Lead and mentor a team of DFX engineers, fostering technical excellence, innovation, and collaboration.
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Manage project priorities, schedules, and deliverables to meet program milestones.
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Recruit, train, and develop engineering talent.
-
DFT Strategy & Execution
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Work collaboratively with CDFX function Leads/Managers to define roadmap and drive DFT methodologies, flows, and best practices for complex CPU/GPU/SoC designs.
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Oversee implementation and verification of DFT RTL build, scan insertion, ATPG, BIST (MBIST, LBIST), boundary scan, and JTAG.
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Ensure seamless integration of DFT architecture into the overall design flow.
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Collaborate with SOC design and product engineering teams to ensure testability, debugability and manufacturability.
-
Technical Ownership
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Provide hands-on guidance in DFT tool and flow usage (Siemens, Synopsys, … etc.) and debug.
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Drive innovation in low-power test methodologies, hierarchical DFT, and advanced fault models.
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Cross-Functional Collaboration
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Partner with architecture, RTL design, verification, and physical design teams to ensure DFX requirements are met.
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Collaborate with SOC design and product engineering teams on strategic initiatives innovative DFT/DFD design solutions to ensure product testability, debuggability, manufacturability and quality.
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Interface with foundry and EDA vendors to adopt and deploy cutting-edge DFT solutions.
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Occasional travel per business need.
PREFERRED EXPERIENCE:
-
A strong leader with experience working with a distributed team
-
Strong mentoring and coaching skills
-
Proven experience managing and leading a medium-sized engineering teams (better with 15-20 staffs)
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Experienced and skilled DFT design or DV on complex CPU/GPU SOC projects
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Strong system and software engineering background
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Strong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers
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Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments
-
Must be a self-starter and self-motivated
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Prior experience Managing technical teams
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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AMDについて

AMD
PublicAdvanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.
10,001+
従業員数
Santa Clara
本社所在地
$240B
企業価値
レビュー
10件のレビュー
3.7
10件のレビュー
ワークライフバランス
2.8
報酬
3.2
企業文化
4.1
キャリア
3.4
経営陣
3.8
68%
知人への推奨率
良い点
Great team culture and spirit
Innovative projects and cutting-edge technology
Supportive management and leadership
改善点
High workload and overwhelming demands
Work-life balance challenges
High pressure and stressful deadlines
給与レンジ
6件のデータ
L2
L6
L3
L4
L5
L2 · Data Analyst L2
0件のレポート
$76,430
年収総額
基本給
$30,572
ストック
$38,215
ボーナス
$7,643
$53,501
$99,359
面接レビュー
レビュー2件
難易度
3.0
/ 5
期間
14-28週間
内定率
50%
面接プロセス
1
Application Review
2
Recruiter Screen
3
Hiring Manager Interview
4
Technical Interview
5
Offer
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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