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求人AMD

IP Verification Lead

AMD

IP Verification Lead

AMD

Bangalore

·

On-site

·

Full-time

·

2mo ago

福利厚生

Learning

Parental Leave

Healthcare

必須スキル

React

TypeScript

JavaScript

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.SMTS SILICON DESIGN ENGINEER

THE ROLE:

The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD So Cs.

THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

  • Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.
  • Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.
  • Quality deliverables through regressions
  • Verification coverage:  code-coverage, functional coverage, assertions, to achieve 100% verification completeness
  • Reviews, and feedback to design/architecture teams.

PREFERRED EXPERIENCE:

  • Years of experience 13+ Required.
  • Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA)
  • Expertise in code and functional coverage.
  • Excellent Problem solving and debugging skills.
  • Excellent Communication skills
  • Strong digital design knowledge.
  • Exposure to UPF based low power RTL verification.
  • Prior experience in leading a team is desirable.
  • Prior experience in PLL verification and Mixed signal verification methodology is highly desirable.
  • Exposure to digital-analog co-simulations (cosims) is desirable.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in Electronics engineering/Electrical Engineering

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

総閲覧数

1

応募クリック数

0

模擬応募者数

0

スクラップ

0

AMDについて

AMD

AMD

Public

Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.

10,001+

従業員数

Santa Clara

本社所在地

$240B

企業価値

レビュー

3.7

10件のレビュー

ワークライフバランス

2.8

報酬

3.2

企業文化

4.1

キャリア

3.4

経営陣

3.8

68%

友人に勧める

良い点

Great team culture and spirit

Innovative projects and cutting-edge technology

Supportive management and leadership

改善点

High workload and overwhelming work demands

Work-life balance challenges

High pressure and stressful deadlines

給与レンジ

6件のデータ

L2

L3

L4

L5

L6

M3

M4

M5

M6

L2 · Graphic Designer L2

0件のレポート

$162,512

年収総額

基本給

$65,005

ストック

$81,256

ボーナス

$16,251

$113,758

$211,266

面接体験

2件の面接

難易度

3.0

/ 5

期間

14-28週間

内定率

50%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Hiring Manager Interview

4

Technical Interview

5

Offer

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving