WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.MTS SILICON DESIGN ENGINEERTHE ROLE:
The Formal Lead Engineer will be responsible for driving the end‑to‑end formal verification strategy for complex IPs and subsystems. This role requires strong ownership of property-based formal verification, the ability to define and optimize formal flows, guide design/verification teams on best practices, and ensure high‑quality formal signoff. The engineer will also mentor and develop junior formal team members, enabling scaled adoption of formal methodologies across the organization.

KEY RESPONSIBILITIES:

• Define the formal verification plan and methodology for assigned IPs or subsystems.
• Identify key design blocks for formal verification.
• Establish scalable formal flows for property-based verification, assertion development, abstraction, and coverage measurement.
• Drive formal convergence through targeted abstraction, constraints, decomposition, and environment modeling.
• Own and deliver final formal signoff, ensuring thorough coverage and verification completeness.
• Build, maintain, and enhance reusable formal verification environments.
• Evaluate new formal technologies and recommend improvements to boost team productivity.
• Provide technical direction and resolve complex verification challenges across the team.
• Collaborate with RTL designers, DV engineers, architects, and methodology teams to ensure seamless integration of formal with simulation/UVM flows.
• Participate in design reviews and influence micro‑architecture for formal‑friendly implementation.

PREFERRED EXPERIENCE:

• 8–16 years of industry experience in formal verification or related verification domains.

• Experience leading or mentoring engineers.

• Exposure to UVM environments and simulation flows is a plus.

• Experience in Memory/PHY/Interface IPs (DDR/HBM/LPDDR/PCIE/AMBA etc.) is an advantage but not mandatory.

• Strong hands‑on expertise with formal verification tools (Synopsys VC Formal, Jasper Gold, Questa Formal / or equivalents).

• Deep understanding of property-based verification, SVA, PSL, proof techniques, formal modeling, abstraction, and coverage.

• Good knowledge of RTL design, digital logic, micro‑architecture, and verification methodologies.

• Experience driving formal signoff independently.

• Excellent problem‑solving ability and strong communication skills.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.