Jobs
Benefits & Perks
•Competitive salary and equity package
•Flexible work arrangements
•Generous paid time off and holidays
•401(k) matching
•Parental leave
•Professional development budget
•Equity
•Flexible Hours
•Parental Leave
•Learning
Required Skills
TypeScript
JavaScript
Python
WHAT YOU DO AT AMD CHANGES EVERYTHING:
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.THE ROLE
The Memory Subsystem team at AMD is hiring a Senior Member of Technical Staff (SMTS) RTL and Integration Engineer to lead the definition, design, development, and integration of high-speed LPDDR/DDR memory subsystem solutions and associated IP.
This role includes technical ownership of key memory subsystem components across multiple product lines and close collaboration with architecture, verification, firmware, BIOS, and physical design teams across geographically distributed sites.
THE PERSON
You are a senior-level RTL and integration engineer with deep technical expertise and a system-level mindset. You are comfortable owning complex blocks or subsystems end to end, driving architecture discussions, and mentoring engineers through execution and debug.
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KEY RESPONSIBILITIES
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Own and drive RTL design and integration for memory subsystem IP and top-level logic
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Lead micro-architecture definition and translate system requirements into robust RTL implementations
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Integrate IP blocks to deliver complete DDR/LPDDR memory subsystems across product lines
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Partner closely with verification teams on test strategy, debug, coverage, and pre-silicon issue resolution
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Collaborate with physical design teams on timing targets, floorplanning, CDC, and clocking strategies
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Drive resolution of complex functional, timing, and integration issues across subsystem boundaries
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Develop and maintain high-quality subsystem documentation, interface definitions, and timing diagrams
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Support pre-silicon and post-silicon bring-up and work with firmware and BIOS teams to enable features
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Mentor and technically guide other engineers, promoting best practices and design quality
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REQUIRED QUALIFICATIONS
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Expert proficiency in Verilog and System Verilog for RTL design
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Extensive experience designing and integrating IP and subsystems in complex SoC environments
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Strong understanding of memory subsystem architecture and micro-architecture
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Expert knowledge of clocking, resets, CDC, and synchronization techniques
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Proven ability to debug complex RTL and integration issues using simulation and emulation tools
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Experience leading technical efforts and collaborating across design, verification, firmware, and physical design teams
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Strong experience using Git and/or Perforce
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PREFERRED EXPERIENCE
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Hands-on experience with DDR/JEDEC standard IP, DDR PHY, memory controllers, or full memory subsystems
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Experience serving as technical owner for subsystem or major IP blocks
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Knowledge of SVA/OVL and synthesizable assertions
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Experience with VCS and Zebu emulation for debug and bring-up
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Strong understanding of power management, UPF, and low-power design techniques
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Experience analyzing system-level performance, power, and architectural tradeoffs
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
LOCATION
Ireland (Dublin or other AMD Ireland locations; hybrid working supported).
Employment is contingent on meeting applicable export control and security requirements.
#Ireland
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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About AMD

AMD
PublicA semiconductor company that designs and develops graphics units, processors, and media solutions
10,001+
Employees
Santa Clara
Headquarters
Reviews
3.5
25 reviews
Work Life Balance
3.2
Compensation
4.1
Culture
3.6
Career
3.4
Management
3.1
65%
Recommend to a Friend
Pros
Good compensation and benefits
Positive work environment
Great management and coworkers
Cons
Poor work life balance
Micromanagement and excessive tracking
Too much pressure and workload
Salary Ranges
6 data points
L2
L3
L4
L5
L6
L2 · Data Analyst L2
0 reports
$76,430
total / year
Base
$30,572
Stock
$38,215
Bonus
$7,643
$53,501
$99,359
Interview Experience
5 interviews
Difficulty
3.6
/ 5
Duration
14-28 weeks
Offer Rate
60%
Experience
Positive 20%
Neutral 20%
Negative 60%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Technical Interview
5
Hiring Manager Interview
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
Past Experience
System Design
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