WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.THE ROLE:

As a senior DFT RTL Design Engineer within the CDFX organization, you will play a critical role in architecting, designing, and delivering production-quality DFT RTL solutions for complex, state-of-the-art So Cs. As technical owner of DFT RTL blocks used across multiple So Cs, you will be responsible for architectural definition, RTL coding and verification, and silicon validation support. This role requires strong hands-on RTL expertise, the ability to work and collaborate with cross-functional teams and strong knowledge and competency debugging issues spanning RTL, netlists, design constraints, and silicon bring-up.

THE PERSON:

You take strong ownership of your work and remain effective in complex, fast‑moving environments. You approach problems with a structured and curious mindset, communicate clearly with diverse stakeholders, and collaborate effectively across teams. You balance execution with long‑term thinking, demonstrate sound judgement under ambiguity, and continuously learn from experience to improve outcomes.

KEY RESPONSIBLITIES:

• Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
• Partner with architecture team to define design improvements, new initiatives that drive our IP forward to achieve best-in-class Scan Coverage, DPPM, and Debug capabilities.
• Support RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
• Work with multi-functional teams to provide IP and SOC integration support, collaboration to develop solutions for complex/unique problems
• Support post-silicon debug, and taking learnings to propose RTL and micro‑architecture improvements
• Clearly document designs, debug findings, and methodology improvements, and communicate status and risks to cross-functional stakeholders.

PREFERRED EXPERIENCE:

• Strong hands-on experience with System Verilog / Verilog RTL design on complex So Cs.
• Demonstrated ability to write clean, scalable, and reusable RTL used across multiple So Cs
• Strong understanding and experience using Lint, CDC, Synthesis, STA tools
• Proven ability to debug issues across RTL, gate-level netlists, constraints, and tool flows.
• Experience working in UNIX/Linux environments, with scripting proficiency in TCL, Perl, or shell.
• Strong collaboration, communication, and ownership mindset in a fast-paced, globally distributed engineering environment.
• Prior experience delivering DFT solutions through full silicon life cycles, from early RTL to post-silicon bring-up and yield ramp, is highly valued.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer Engineering/ Electrical Engineering

LOCATION:

Markham, Ontario CA

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

As a senior DFT RTL Design Engineer within the CDFX organization, you will play a critical role in architecting, designing, and delivering production-quality DFT RTL solutions for complex, state-of-the-art So Cs. As technical owner of DFT RTL blocks used across multiple So Cs, you will be responsible for architectural definition, RTL coding and verification, and silicon validation support. This role requires strong hands-on RTL expertise, the ability to work and collaborate with cross-functional teams and strong knowledge and competency debugging issues spanning RTL, netlists, design constraints, and silicon bring-up.

THE PERSON:

You take strong ownership of your work and remain effective in complex, fast‑moving environments. You approach problems with a structured and curious mindset, communicate clearly with diverse stakeholders, and collaborate effectively across teams. You balance execution with long‑term thinking, demonstrate sound judgement under ambiguity, and continuously learn from experience to improve outcomes.

KEY RESPONSIBLITIES:

• Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
• Partner with architecture team to define design improvements, new initiatives that drive our IP forward to achieve best-in-class Scan Coverage, DPPM, and Debug capabilities.
• Support RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
• Work with multi-functional teams to provide IP and SOC integration support, collaboration to develop solutions for complex/unique problems
• Support post-silicon debug, and taking learnings to propose RTL and micro‑architecture improvements
• Clearly document designs, debug findings, and methodology improvements, and communicate status and risks to cross-functional stakeholders.

PREFERRED EXPERIENCE:

• Strong hands-on experience with System Verilog / Verilog RTL design on complex So Cs.
• Demonstrated ability to write clean, scalable, and reusable RTL used across multiple So Cs
• Strong understanding and experience using Lint, CDC, Synthesis, STA tools
• Proven ability to debug issues across RTL, gate-level netlists, constraints, and tool flows.
• Experience working in UNIX/Linux environments, with scripting proficiency in TCL, Perl, or shell.
• Strong collaboration, communication, and ownership mindset in a fast-paced, globally distributed engineering environment.
• Prior experience delivering DFT solutions through full silicon life cycles, from early RTL to post-silicon bring-up and yield ramp, is highly valued.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer Engineering/ Electrical Engineering

LOCATION:

Markham, Ontario CA

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.