Back

CPU Design Verification Architect (Unit Level)

JOB_DESCRIPTION.SHARE.HTML
CAROUSEL_PARAGRAPH

• JOB_DESCRIPTION.SHARE.HTML
• Bangalore, India
• Engineering
• 74299

mail_outline
Get future jobs matching this search
Loginor Register

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

PMTS SILICON DESIGN ENGINEER:

THE ROLE:

We are seeking a highly skilled Verification Engineer who can carry out cutting-edge unit-level verification for complex CPU designs. You will own the creation of comprehensive test plans, drive coverage closure, and collaborate closely with RTL designers to resolve issues and achieve tape-out readiness. Beyond simulation, you will support emulation and post-silicon validation efforts, while setting best practices and mentoring junior engineers to elevate the team’s verification capabilities.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

Experienced verification engineer with deep expertise in high-performance CPU verification. Proven track record in developing scalable verification environments, driving coverage closure, and collaborating across architecture, RTL, and post-silicon teams.

Key Responsibilities:

• Architect and implement unit-level verification environments using C++/System Verilog/UVM
• Develop detailed test plans for functional and performance verification of Load/Store, Scheduler, and Execute Units
• Create directed and random stimulus, checkers, and coverage models
• Debug simulation failures and collaborate with RTL designers to resolve issues
• Drive coverage closure and ensure high-quality tape-out readiness
• Support emulation and post-silicon validation efforts
• Mentor junior engineers and contribute to verification best practices

Qualifications:

• 16+ years of experience in CPU verification, with focus on module-level DV
• Strong understanding of out-of-order execution, memory ordering, and cache coherence
• Proficiency in System Verilog, UVM, C++, Python
• Experience with x86, ARM, or RISC-V architectures
• Familiarity with simulation tools (VCS, Verilator), waveform debugging, and scripting etc
• Excellent problem-solving and communication skills

CTERR1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
Apply JOB_DESCRIPTION.SHARE.HTML
CAROUSEL_PARAGRAPH
JOB_DESCRIPTION.SHARE.HTML