招聘
福利待遇
•Parental Leave
•Healthcare
必备技能
Verilog
SystemVerilog
C++
Python
WHAT YOU DO AT AMD CHANGES EVERYTHING:
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.THE ROLE
We are looking for an adaptive, self-motivated Design Engineer to work on IP (Intellectual Property) Release and Verification processes. As a key contributor in Infinity (Data) Fabric IP, you will be the critical link between the core IP development team and the various System-on-Chip (SoC) product integration teams. You will assist in preparing IP releases, validating deliverables and ensure that the IP milestone drops are high-quality, fully documented, and meet critical SoC project schedule. You will also be providing first-level support for integration issues, debug and analysis for failures.
THE PERSON
You are a detail-oriented engineer with a passion for modern, complex processor architecture, digital design, and/or verification in general. You have strong analytical and problem-solving skills and comfortable using industry-standard tools to ensure smooth IP integration. You are a team player who has excellent communication skills and enjoys collaborating with other engineers from different sites/time zones in a fast-paced environment.
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KEY RESPONSIBILITIES
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Collaborate with architects, IP designers, verification, physical design, and program management teams to understand new features, ensure smooth integration and timely deliver
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Build test plan documentation, accounting for interactions with other hardware/software features/components
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Write and implement both directed and random verification tests
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IP Release support: milestone drop delivery to SoC team. Ensure deliverables are complete, accurate, and meet project timelines
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Integration issue triage**:** provide first level of support for integration-related issues, helping to identify whether problems originate from IP, flow, or environment
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Debug & Analysis: Use simulation and debug tools (e.g., VCS, Verdi) to analyze failures and support root cause identification
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Work with RTL and firmware engineers to resolve design defects
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Maintain and update IP documentation, including release details, integration guidelines, feature lists and known issues
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Ensure changelist integration
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Support automation efforts using scripting languages (Python, Perl) to improve release and validation flows.
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PREFERED EXPERIENCE
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Good understanding of computer architecture, interconnects and cache coherency
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Experience with digital design and verification methodologies, such as UVM
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Ability to analyze simulation results and assist in resolving complex technical issues
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Familiarity with simulation, emulation, and debug tools (e.g., VCS, Verdi)
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Object‑oriented programming experience (C++ and System Verilog)
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Scripting skills in Python, Perl, Shell, or Ruby
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Experience working in a Unix/Linux environment.
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NICE TO HAVE
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Direct experience with Verilog simulators (Model Sim, VCS, Eda Playground, etc.)
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Exposure to scripting and automation tools to streamline and enhance modeling workflows
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Familiarity with formal verification concepts and tools is a plus.
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PERSONAL COMPETENCIES
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Analytical mindset; goal‑oriented and eager to learn
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Self‑driven while able to work effectively within a team
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High sense of ownership and personal accountability
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Excellent communication and collaboration skills in a global, cross‑functional environment.
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ACADEMIC CREDENCIALS
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Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related discipline.
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LOCATION
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Iași (Hybrid)
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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关于AMD

AMD
PublicAdvanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.
10,001+
员工数
Santa Clara
总部位置
$240B
企业估值
评价
3.7
10条评价
工作生活平衡
2.8
薪酬
3.2
企业文化
4.1
职业发展
3.4
管理层
3.8
68%
推荐给朋友
优点
Great team culture and spirit
Innovative projects and cutting-edge technology
Supportive management and leadership
缺点
High workload and overwhelming work demands
Work-life balance challenges
High pressure and stressful deadlines
薪资范围
6个数据点
L2
L3
L4
L5
L6
L2 · Data Analyst L2
0份报告
$76,430
年薪总额
基本工资
$30,572
股票
$38,215
奖金
$7,643
$53,501
$99,359
面试经验
2次面试
难度
3.0
/ 5
时长
14-28周
录用率
50%
面试流程
1
Application Review
2
Recruiter Screen
3
Hiring Manager Interview
4
Technical Interview
5
Offer
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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