WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.THE ROLE:

We are seeking a seasoned SoC PD lead with expertise in delivering high-quality physical design implementations that meet PPA and schedule targets, contribute to physical design innovation, influencing multiple programs and organizational decisions, meticulous about Power, Performance and Area while driving schedule and managing cost.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Own end-to-end physical design for high-performance, low-power So Cs, including floorplanning, placement, clock tree synthesis, routing, and timing closure.

• Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm), balancing performance, power, and area (PPA).

• Establish and drive sign-off criteria and waiver processes.

• Introduce innovative techniques for congestion management, timing optimization, and power integrity.

• Partner with RTL, architecture, CAD, and verification teams to resolve design challenges and ensure seamless integration.

• Influence design partitioning, interface planning, and hierarchical strategies to meet aggressive schedules.

• Anticipate schedule risks tied to ECO delivery and resource constraints; implement prefetch and compliance gates for ECO readiness.

• Publish risk burndown reports and mitigation plans for tapeout-critical paths.

• Lead technical reviews and provide consultative input to management on design trade-offs.

• Work closely with Design teams for Area and Floorplan refinement, Timing targets, Pre-Si bug resolution and PPA sign-off.

PREFERRED EXPERIENCE:

• 15+ Years of experience in relevant domain.
• Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.
• Foundational experience in SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks & Resets.
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

We are seeking a seasoned SoC PD lead with expertise in delivering high-quality physical design implementations that meet PPA and schedule targets, contribute to physical design innovation, influencing multiple programs and organizational decisions, meticulous about Power, Performance and Area while driving schedule and managing cost.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Own end-to-end physical design for high-performance, low-power So Cs, including floorplanning, placement, clock tree synthesis, routing, and timing closure.

• Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm), balancing performance, power, and area (PPA).

• Establish and drive sign-off criteria and waiver processes.

• Introduce innovative techniques for congestion management, timing optimization, and power integrity.

• Partner with RTL, architecture, CAD, and verification teams to resolve design challenges and ensure seamless integration.

• Influence design partitioning, interface planning, and hierarchical strategies to meet aggressive schedules.

• Anticipate schedule risks tied to ECO delivery and resource constraints; implement prefetch and compliance gates for ECO readiness.

• Publish risk burndown reports and mitigation plans for tapeout-critical paths.

• Lead technical reviews and provide consultative input to management on design trade-offs.

• Work closely with Design teams for Area and Floorplan refinement, Timing targets, Pre-Si bug resolution and PPA sign-off.

PREFERRED EXPERIENCE:

• 15+ Years of experience in relevant domain.
• Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.
• Foundational experience in SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks & Resets.
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.