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求人AMD

Staff Analog Layout Design Engineer

AMD

Staff Analog Layout Design Engineer

AMD

Penang

·

On-site

·

Full-time

·

2mo ago

福利厚生

Healthcare

Parental Leave

必須スキル

CMOS

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.THE ROLE:
AMD is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting-edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signalling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

THE PERSON: An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.

KEY RESPONSIBILITIES:

  • Layout of basic digital and analog building blocks using analog transistor level components.
  • Layout of analog macros, power pads, and input/output pads using above blocks
  • Working closely with Analog designers in floorplanning; power grid and signal flow planning
  • Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
  • Creation of blackbox models for other groups in the design flow

PREFERRED EXPERIENCE:

  • Must have detailed knowledge of CMOS circuit theory.
  • Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
  • Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
  • Must have at least 5 years of relevant or comparable experience doing analog layout design
  • Knowledge of chip level integration and ESD concepts a plus
  • Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
  • Good understanding of signal and clock shielding and isolation techniques
  • Ability to work well as part of a team

ACADEMIC CREDENTIALS:

  • Bachelor’s degree in Engineering (or related field) OR Associates Degree in Engineering.

LOCATION: Penang, Malaysia

DV

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

総閲覧数

1

応募クリック数

0

模擬応募者数

0

スクラップ

0

AMDについて

AMD

AMD

Public

Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.

10,001+

従業員数

Santa Clara

本社所在地

$240B

企業価値

レビュー

3.7

10件のレビュー

ワークライフバランス

2.8

報酬

3.2

企業文化

4.1

キャリア

3.4

経営陣

3.8

68%

友人に勧める

良い点

Great team culture and spirit

Innovative projects and cutting-edge technology

Supportive management and leadership

改善点

High workload and overwhelming work demands

Work-life balance challenges

High pressure and stressful deadlines

給与レンジ

6件のデータ

L2

L3

L4

L5

L6

L2 · Data Analyst L2

0件のレポート

$76,430

年収総額

基本給

$30,572

ストック

$38,215

ボーナス

$7,643

$53,501

$99,359

面接体験

2件の面接

難易度

3.0

/ 5

期間

14-28週間

内定率

50%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Hiring Manager Interview

4

Technical Interview

5

Offer

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving