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Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Join our ambitious team at Micron, where you will have the outstanding opportunity to define micro‑architecture for base‑die digital subsystems, including high‑bandwidth memory (HBM) channel support logic, initialization and boot sequencing, training orchestration, configuration and control registers (CSR), telemetry, performance counters, and reliability features such as error logging and recovery sequencing.
Responsibilities:
- Translate system requirements into timing, power, and area budgets with physical layer (PHY) and system architects, and maintain interface specifications for bus protocols, clock‑domain crossing (CDC) strategy, and reset strategy.
- Implement synthesizable register‑transfer level (RTL) builds in System Verilog and integrate multi‑channel logic, including interrupts, events, register maps, scan hooks, and design‑for‑test (DFT) interfaces.
- Ensure stable reset and power‑up behavior, support corner‑case handling, and maintain clear engineering change order (ECO) pathways.
- Collaborate with design verification (DV) teams to develop verification plans, achieve coverage goals, complete CDC and reset‑domain crossing (RDC) checks, and debug RTL, testbench, and gate‑level issues.
- Provide advice regarding timing constraints for clocks, exceptions, and path intent, and optimize micro‑architecture to manage timing‑critical paths.
- Partner with DFT and test teams to integrate scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST), boundary access, and debug instrumentation.
- Support post‑silicon validation by supplying debug hooks, correlating issues to RTL or architecture, and enabling efficient issue resolution.
Minimum Qualifications
- Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering or Computer Engineering.
- Typically 10+ years in digital build or system‑on‑chip (SoC) integration with ownership of complex logic through tape‑out.
- Expertise in System Verilog RTL build, integration, and debug; clock and reset architecture; CDC and RDC methodologies; and low‑power design concepts such as clock gating and power‑state management.
- Knowledge of design‑for‑debug and design‑for‑test fundamentals and experience managing multi‑functional technical efforts.
Preferred Qualifications
- Experience supporting post‑silicon validation through debug correlation and structured issue resolution.
- Background integrating scan, MBIST, LBIST, and related DFT or debug features.
- Experience developing verification plans and partnering with DV teams to reach coverage goals.
- Ability to refine micro‑architecture to improve timing and offer mentorship on constraints.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert**:** Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
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About Micron

Micron
PublicMicron Technology is a global leader in memory and storage solutions, manufacturing DRAM, NAND flash memory, and solid-state drives for computing, mobile, automotive, and data center applications.
10,001+
Employees
Boise
Headquarters
$100B
Valuation
Reviews
3.5
3 reviews
Work Life Balance
2.0
Compensation
4.0
Culture
2.0
Career
4.0
Management
1.5
Pros
Good learning opportunities
High salary/good pay
Multiple positions available
Cons
Poor work-life balance
Excessive overtime
Management disagreements
Salary Ranges
37 data points
Junior/L3
Mid/L4
Junior/L3 · Business Intelligence Analyst
1 reports
$115,042
total / year
Base
$100,037
Stock
-
Bonus
-
$115,042
$115,042
Interview Experience
4 interviews
Difficulty
2.8
/ 5
Duration
14-28 weeks
Offer Rate
25%
Experience
Positive 25%
Neutral 25%
Negative 50%
Interview Process
1
Application Review
2
Recruiter/Phone Screen
3
Technical Interview
4
Final Round Interview
5
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
Past Experience
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