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Benefits & Perks
•Professional development budget
•Team events and activities
•401(k) matching
•Comprehensive health, dental, and vision insurance
•Flexible work arrangements
•Competitive salary and equity package
•Learning
•Healthcare
•Flexible Hours
•Equity
Required Skills
Python
JavaScript
Node.js
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Software Engineer — Low-Power Verification (Palladium & Protium)
We are seeking a highly skilled
Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this role, you will drive innovations that improve the debuggability, performance, and scalability of multi-billion-gate UPF (Unified Power Format) designs across modular compilation flows (2-state and 4-state).
Key Responsibilities
-
Design, develop, and optimize low-power verification software for Palladium and Protium.
-
Improve UPF design debuggability within the IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state).
-
Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
-
Collaborate closely with R&D,Product Engineering (PE), and Application Engineering (AE) to deploy UPF solutions across diverse flows, including:
-
AVIP UPF 2/4-state
-
UVMA UPF 2/4-state
-
MC UPF
-
Dielets UPF
-
Consolidate and unify UPF software across Palladium and Protium platforms.
-
Contribute to major initiatives such as:
-
MC PPC flow with UPF 4-state
-
UPF compilation time optimization
-
Full Vision UPF probe integration
-
SAGE UPF debug with Verisium
Qualifications
- Bachelor’s degree in Computer Science or Electrical Engineering with 7 years of relevant experience,
OR a Master’s degree with5 years,
OR a PhD with1 year of industry experience.
Required Skills
- Strong proficiency in object-oriented design and C development.
- Experience with standard C/C libraries and the C STL.
- Demonstrated ability to build high-performance software for large-scale data processing.
- Scripting experience in Perl,Tcl/Tk, and/or Python.
- Familiarity with IEEE 1801 and UPF implementation.
- Experience with Verilog,System Verilog, and VHDL.
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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About Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
Employees
San Jose
Headquarters
Reviews
3.3
7 reviews
Work Life Balance
2.0
Compensation
2.5
Culture
1.8
Career
2.0
Management
1.5
15%
Recommend to a Friend
Pros
Built strong client relationships
Useful for repetitive tasks
Employment opportunities
Cons
Poor management and micromanagement
Lack of career growth opportunities
Technical architecture and code quality issues
Salary Ranges
65 data points
Junior/L3
Junior/L3 · Data Analyst
1 reports
$91,103
total / year
Base
$85,276
Stock
-
Bonus
$5,827
$59,612
$139,984
Interview Experience
1 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
Common Questions
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
News & Buzz
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