We are seeking an experienced Hardware Emulation Engineer to lead the deployment, optimization, and debug of large-scale SoC designs on hardware emulation platforms such as Synopsys ZeBu, Siemens Veloce, or Cadence Palladium.

You will collaborate closely with design, verification, software, and validation teams to accelerate pre-silicon bring-up, software development, and system-level power and performance analysis.

As a senior contributor, you will also mentor junior engineers, drive emulation methodologies, and help define flows that improve debug efficiency and turnaround time.

Key Responsibilities

• Lead emulation compilation, partitioning, mapping, and bring-up of sophisticated SoC and subsystem RTL designs.
• Develop and maintain automated emulation flows and scripts (TCL, Python, Makefiles).
• Collaborate across RTL, verification, and software teams to integrate IP, debug issues, and enable pre-silicon software bring-up.
• Implement and optimize transactors, virtual bridges, and hybrid co-simulation for software execution.
• Work with EDA vendors to evaluate new emulator features and drive performance improvements
• Mentor junior engineers on flows and methodologies.

Required Qualifications

• Degree in Electronics, Computer Engineering, or equivalent – with 4-8 years of experience in ASIC/SoC verification or emulation.
• Hands-on experience with at least one major emulation platform from EDA vendors like Synopsys, Siemens or Cadence.
• Strong RTL, synthesis, and timing knowledge (SystemVerilog/Verilog/VHDL).
• Proficient in debug tools and waveform analysis (SimVision, Verdi, or DVE).
• Solid understanding of transactors and standard interfaces (AXI, PCIe, DDR, USB, Ethernet, etc.).
• Skilled in C/C++, scripting and automation (Python, Perl, or TCL).
• Familiar with SystemVerilog testbenches, acceleration, and SoC boot flows.
• Experience with CPUs and SoC boot flows, and firmware loading.
• Excellent problem-solving and cross-team collaboration skills.

Good-to-have Qualifications

• Experience with hybrid emulation (Palladium/Protium) or FPGA prototyping flows.
• Knowledge of performance and power validation in emulation environments.
• Experience with multi-clock domain designs and CDC debug.
• Familiarity with CI/CD automation (Jenkins, GitLab CI) for emulation regression management.
• Leadership experience mentoring junior engineers or leading small teams.

Key Success Attributes

• Strong ownership and ability to deliver under tight schedules.
• Ability to drive complex SoC debug through detailed analysis and cross-team coordination.
• Continuous improvement attitude for emulation performance, stability, and usability.
• Excellent communication and documentation skills.

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Accommodations at Arm

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Hybrid Working at Arm

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Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.