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CPU CDC/RDC/STA Engineer

Apple

CPU CDC/RDC/STA Engineer

Apple

Beaverton, OR

·

On-site

·

Full-time

·

1mo ago

Benefits & Perks

Professional development budget

401(k) matching

Competitive salary and equity package

Comprehensive health, dental, and vision insurance

Generous paid time off and holidays

Team events and activities

Learning

Equity

Healthcare

Required Skills

React

Python

Node.js

CPU CDC/RDC/STA Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!

About the Role

As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites.

Responsibilities

In this role, you will be:

  • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
  • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
  • Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue
  • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs including things needed to complement CDC/RDC
  • Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
  • Working closely with EDA vendor representatives to drive improvements and new methodologies
  • Working closely with RTL, Verification, CAD, and Physical Design teams

Minimum Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC)
  • Experience with at least one of the following: Synopsys or Real Intent tool
  • Scripting experience in TCL or Perl
  • Experience in Verilog

Preferred Qualifications

  • Experience in System Verilog Assertions (SVA) and Design Verification (DV) Simulations
  • Experience in multi-clock-domain RTL design
  • Knowledge in Spyglass, VC-Static, Prime Time, or Meridian is a plus

Equal Opportunity

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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About Apple

Apple

Apple

Public

A technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.

10,001+

Employees

Cupertino

Headquarters

$3.5T

Valuation

Reviews

4.0

10 reviews

Work Life Balance

4.0

Compensation

4.2

Culture

3.8

Career

3.5

Management

3.2

75%

Recommend to a Friend

Pros

Great coworkers and people

Excellent benefits and perks

Fast-paced and engaging work environment

Cons

High expectations and pressure

Management quality varies

Limited career progression opportunities

Salary Ranges

17,968 data points

L2

L3

L4

L5

L6

M3

M4

M5

M6

L2 · Industrial Designer L2

0 reports

$320,450

total / year

Base

$128,180

Stock

$160,225

Bonus

$32,045

$224,315

$416,585

Interview Experience

5 interviews

Difficulty

3.4

/ 5

Duration

28-42 weeks

Offer Rate

20%

Experience

Positive 20%

Neutral 40%

Negative 40%

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Behavioral Interview

5

Onsite/Virtual Interviews

6

Team Matching

7

Offer

Common Questions

Coding/Algorithm

System Design

Behavioral/STAR

Technical Knowledge

Culture Fit