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Back Packaging EngineerJOB_DESCRIPTION.SHARE.HTMLCAROUSEL_PARAGRAPHJOB_DESCRIPTION.SHARE.HTMLHsinchu, Taiwan Engineering76274mail_outline Get future jobs matching this search Loginor Register Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:Candidate is required to work closely with oSATs and cross-functional teams to bring up and sustain for FOPLP, InFO, Co WoS-L,Co WoS-S, WLFO packages. THE PERSON:The ideal candidate will have a balanced mix of strong technical knowledge as well as program management experience in FOPLP, InFO, Co WoS-L,Co WoS-S, WLFO package functions. The successful candidate must be a team player with a commitment to meeting deadlines. Lead & drive for solutions with an aptitude to thrive in a fast-paced multi-tasking environment. He or she would have excellent cross functional project management skill, with strong interpersonal skills and good communication & presentation skills. He or she must have good command of both written and spoken English. KEY RESPONSIBILITIES:Responsible for FOPLP, InFO, Co WoS-L, Co WoS, WLFO package Manufacturing readiness for New Product bring up at manufacturing site. Responsible for packaging yield, quality, cost and operation productivity improvements and sustaining activities. Drive assembly process baseline standardization and continuous improvement.
Responsible for the packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, Functional Test and Mark/Pack.
Drive Assembly manufacturer to enhance process, equipment & material capability for future generation/technology products Co-work with Packaging BU on NPI and Ramp Up readiness at manufacturing site. Proactively follow up task assignments and report status timely to stakeholders.
Responsible to manage performance of assembly manufacturing site/supplier regarding yield & quality, out of control lot disposition, and any outliers with close loop on reporting.
The role will require working together with both internal engineering counterparts & extensive interactions within the Package engineering organization, and interacting with several other internal organizations (procurement, supply chain, reliability, etc.) on program deliverables with accurate and timely reporting of program status with executive summary update throughout its life cycle.
Responsible for strategic supplier management.
Plan and execute change management from internal or external parties.
Assist in additional duties as deemed fit by supervisor. Job may include other duties as assigned/ deemed fit by supervisor. PREFERRED EXPERIENCE:Min 5 years’ experience in InFO or 2.5D/3D Bump/TSV/Packaging, Flip Chip BGA/LGA or WLFO process engineering with min total 7 years
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About AMD

AMD
PublicA semiconductor company that designs and develops graphics units, processors, and media solutions
10,001+
Employees
Santa Clara
Headquarters
Reviews
3.5
25 reviews
Work Life Balance
3.2
Compensation
4.1
Culture
3.6
Career
3.4
Management
3.1
65%
Recommend to a Friend
Pros
Good compensation and benefits
Positive work environment
Great management and coworkers
Cons
Poor work life balance
Micromanagement and excessive tracking
Too much pressure and workload
Salary Ranges
6 data points
L2
L3
L4
L5
L6
M3
M4
M5
M6
L2 · Graphic Designer L2
0 reports
$162,512
total / year
Base
$65,005
Stock
$81,256
Bonus
$16,251
$113,758
$211,266
Interview Experience
5 interviews
Difficulty
3.6
/ 5
Duration
14-28 weeks
Offer Rate
60%
Experience
Positive 20%
Neutral 20%
Negative 60%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Technical Interview
5
Hiring Manager Interview
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
Past Experience
System Design
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