招聘
Benefits & Perks
•Professional development budget
•Team events and activities
•401(k) matching
•Comprehensive health, dental, and vision insurance
•Parental leave
•Learning
•Healthcare
•Parental Leave
Required Skills
Python
JavaScript
TypeScript
WHAT YOU DO AT AMD CHANGES EVERYTHING:
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.SENIOR MANAGER SILICON DESIGN ENGINEER
THE ROLE (SOC Lead):
Drive and lead end-to-end SOC/ASIC execution working with functional teams like Design, DFT, Verification, Physical Design to drive execution from concept to tape-out.
Driving Silicon checkout and debug at ATE for Si bring up and taking it forward for ramp to production.
Interface to System and SW engineering teams for successful product delivery to customer.
Drive SOC from concept to productization. Work with customer requirements on product definition, feature, bounding box analysis and drive optimal solution.
Work with business and design team on optimal development cost solution considering in die size, power, performance optimization.
Work with architecture team on high level arch and u Arch definition.
Work with IP team for IP requirements, deliverables and negotiations.
Work with program management team for SOC planning, schedule, resource demand/supply, critical path analysis, dev cost and execution.
Work with SOC functional teams (Design, DFT, DV, PD), System/SW teams to deliver next gen high performance SOC/ASIC designs.
THE PERSON:
Leader with strong self-driving ability and winning attitude.
Need excellent communication skills, both written and oral.
Strong interpersonal and stakeholder management skills.
Strong problem-solving skills.
KEY RESPONSIBILITIES:
Contribute to Bounding box analysis, Design, DFT, Verification, Test-plan, Power Reduction, Timing Convergence & Floorplan, Tape-outs, System engineering and SW deliverables.
Driving SOC cross-site execution from concept to tape-out and productization.
Running regular execution meetings, scrums, standing meetings and resolving bottlenecks.
Project planning, schedule, deliverables, risk/ mitigations. Presenting status update to senior executives.
PREFERRED EXPERIENCE:
20+ years full-time experience in SOC development and delivery.
- Experience of successfully leading *couple of SOC execution from spec to tape-out and productization.
Expertise in SOC integration and implementation
- IP Integration, SOC fabrics, Voltage / Clock domain crossings, DFT, Power intent design, RTL Quality checks, Clock, Reset, Fuses, Synthesis, Timing Analysis, Design Partitioning, PPA optimization, PnR, Timing analysis, Floorplan convergence, Physical design implementation and signoff.
Experience in ASIC execution, customer engagement, deliverables and ASIC execution flow.
Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture.
Strong hands-on experience in different SOC design activities, Verification aspects, Test plan review, Debug/triage, bottleneck resolution etc.
Strong Problem Solving and Debugging Skills:
Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis DC/FC, ICC, and Physical design implementation/signoff tools.
Expertise in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory etc.)
Good understanding of System integration, multi-die methodology, packaging, yield, and system solution.
Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus.
Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks, and mitigation plan.
Comfort with Scripting such as Perl, shell, Python and TCL is a plus.
ACADEMIC CREDENTIALS:
~20+ years of strong experience in leading end to end SOC and ASIC execution.
BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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About AMD

AMD
PublicA semiconductor company that designs and develops graphics units, processors, and media solutions
10,001+
Employees
Santa Clara
Headquarters
Reviews
3.5
25 reviews
Work Life Balance
3.2
Compensation
4.1
Culture
3.6
Career
3.4
Management
3.1
65%
Recommend to a Friend
Pros
Good compensation and benefits
Positive work environment
Great management and coworkers
Cons
Poor work life balance
Micromanagement and excessive tracking
Too much pressure and workload
Salary Ranges
6 data points
L2
L3
L4
L5
L6
L2 · Data Analyst L2
0 reports
$76,430
total / year
Base
$30,572
Stock
$38,215
Bonus
$7,643
$53,501
$99,359
Interview Experience
5 interviews
Difficulty
3.6
/ 5
Duration
14-28 weeks
Offer Rate
60%
Experience
Positive 20%
Neutral 20%
Negative 60%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Technical Interview
5
Hiring Manager Interview
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
Past Experience
System Design
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