Back

Senior ASIC RTL Design Engineer

JOB_DESCRIPTION.SHARE.HTML
CAROUSEL_PARAGRAPH

• JOB_DESCRIPTION.SHARE.HTML
• Santa Clara, California
• Engineering
• 76330
• USD $191,040.00/Yr.
• USD $286,560.00/Yr.

mail_outline
Get future jobs matching this search
Loginor Register

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

As a member of the AMD, you will help bring to life cutting-edge designs and deliver IPs to SOC. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role.

KEY RESPONSIBLITIES:

• RTL design of high speed design, clock/reset/power features, IP Integration, sub-system level design

• Architect and design of power management features.

• Design optimization for implementing power efficient IP, implementing the RTL using low power techniques

• Responsible for the inter IP integration issues resolution

• Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.

• Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design

• Architecting, micro-architecting and documentation of the design features

• Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.

PREFERRED EXPERIENCE:

• Extensive experience in Digital IP/ASIC design and Verilog RTL development

• Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification.

• Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.

• Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.

Should possess expertise in front-end EDA tools sign-off and its flows.

• Familiarity with low power design and low power flow is an added plus.

• Ability to program with scripting languages such as Python or Perl is a plus;

• Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;

• Proven interpersonal skills, leadership and teamwork;

• Excellent writing skills in the English language, editing and organizational skills required;

Skilled at prioritization and multi-tasking;

• Good understanding of engineering terminology used within the semiconductor industry;

Good understanding of digital design concepts;

• Knowledge of, or experience in, functional design verification or design is highly desired.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

This role is not eligible for visa sponsorship.

LOCATION: Santa Clara, CA

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
Apply JOB_DESCRIPTION.SHARE.HTML
CAROUSEL_PARAGRAPH
JOB_DESCRIPTION.SHARE.HTML