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Memory PHY RTL Design Lead

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• JOB_DESCRIPTION.SHARE.HTML
• MARKHAM, Canada
• Engineering
• 76040
• CAD $187,200.00/Yr.
• CAD $280,800.00/Yr.

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Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

The Memory PHY team is looking for a highly skilled Senior / Lead Design Engineer for RTL development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:

You are an experienced digital design engineer with deep knowledge of DDR PHY/controller architecture and JEDEC specifications. You are comfortable taking technical ownership, making architectural decisions, and mentoring others. You are a self-starter who can introduce and deploy new EDA tools and flows into the design environment. You communicate clearly, collaborate effectively across disciplines, and enjoy solving complex technical and methodological problems.

KEY RESPONSIBILITIES:

• Own microarchitectural design and RTL implementation of major IP features and sub-systems.
• Synthesis, STA, CDC/RDC, UPF Design/Simulation, Power optimization, Gate sim.
• Drive PHY digital architecture development from pathfinding and high-level architecture to RTL coding, verification, and support for physical implementation.
• Interpret and apply JEDEC DDR/LPDDR specifications to ensure standards-compliant PHY and controller behavior.
• Collaborate closely with the Firmware team to define, implement, and optimize firmware sequences and algorithms.
• Analyze RTL design for power, performance, and area (PPA); guide optimization strategies and tradeoffs.
• Partner with Design Verification teams to define verification strategies and ensure robust coverage of design features (including UVM-based environments).
• Drive timing synthesis, constraints definition, and support backend teams through physical implementation and signoff.
• Lead and participate in design specification reviews, microarchitecture reviews, and RTL code reviews; enforce high-quality design practices.
• Introduce, evaluate, and deploy new EDA tools, scripts, and methodologies into the workflow to improve productivity and quality.
• Provide technical leadership, mentorship, and day-to-day guidance to junior and intermediate engineers.
• Collaborate with cross-functional teams (architecture, analog/mixed-signal, PD, FW, verification) to resolve complex integration issues.

PREFERRED EXPERIENCE:

• Solid industry experience in digital design engineering, with a focus on complex SoC/IP blocks.

• Strong experience with DDR / LPDDR PHY and/or Memory Controller design, including:

• Good working knowledge of JEDEC DDR/LPDDR specifications.

• Experience translating spec requirements into microarchitecture and RTL.

• Excellent knowledge of Verilog and System Verilog for design; C/C++ experience is a strong plus.

• Proficient with scripting for automation and flow development; experience with Python is preferred.

• Demonstrated ability to bring up and deploy new EDA tools and methodologies into an existing design flow (e.g., lint/CDC/Formal, power analysis, synthesis, static timing, coverage, regression infrastructure).

• Proficient in debugging firmware and RTL code using simulation and waveform tools.

• Experience working with UVM testbenches and verification environments.

• Comfortable working in Linux-based development environments; familiarity with Windows is a plus.

• Knowledge of clocking architectures, synchronization techniques, and CDC (Clock Domain Crossing) methodology.

• Strong understanding of computer organization and microarchitecture.

• Mixed-signal RTL experience (e.g., interfaces to analog front-ends, calibration/control logic) is a plus.

• Demonstrate leadership experience:

• Leading small design teams or technical sub-projects.

• Providing mentorship, code reviews, and technical guidance to junior engineers.

• Influencing architectural and methodology decisions.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Markham, Vancouver

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
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