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Senior Power & Performance Modeling Engineer (UPFM)

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• JOB_DESCRIPTION.SHARE.HTML
• Bangalore, India
• Engineering
• 75833

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Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Role SummaryAMD is seeking a highly motivated engineer to drive the next generation of Unified Power-Frequency Modeling (UPFM) used across our CPU, GPU, and APU product roadmap. The ideal candidate will be passionate about bridging pre-silicon architecture modeling, post-silicon measurement, and system-level power optimization, helping AMD deliver industry-leading performance-per-watt in modern compute platforms.

This role provides a unique opportunity to operate across the full silicon lifecycle—developing analytical models, integrating silicon calibration data, and enabling productization of advanced adaptive power features such as AVFS, hierarchical binning, and chiplet-level optimization.

You will be a core contributor to UPFM evolution, ensuring that predictive modeling, silicon telemetry, and field data are tightly coupled in a continuously-learning modeling pipeline.

• Key Responsibilities

• Expand UPFM to incorporate emerging IPs, new technology nodes, aging models, and hierarchical SoC/power-management structures.

• Build parameterized analytical models capturing:

• Dynamic and static power,

• Voltage–frequency scaling,

• Critical-path delay and FO2-based timing,

• Workload-dependent switching behavior,

• Process variation effects (leakage, Vmin, RC, mobility).

• Integrate silicon data into model calibration loops; refine UPFM coefficients across product generations.

• Develop modeling infrastructure to support early-stage architecture planning and power budgeting. Also enable the evaluation of ROI of new power features and power-delivery innovations.

• Work closely with architecture, design, firmware, and production teams to ensure modeling accuracy and feature success.

• Support product engineers in chiplet binning, AVFS tuning, yield/power analysis, and field-return analysis.

• Collaborate with system teams to extend UPFM for chiplet-based systems and datacenter power constraints.

• Develop and maintain Python/Ruby-based modeling pipelines, data-processing infrastructure, and visualization dashboards.

• Automate ingestion of silicon data into UPFM to support continuous model evolution.

• Build scripts for sensitivity analysis, Monte Carlo modeling, regression, and parametric sweep automation.

• Preferred Experience Candidates with expertise in one or more of the following are strongly encouraged to apply:

Power & Performance Modeling:

• Experience modeling power for digital/analog IPs (CPUs, GPUs, accelerators).

• Familiarity with switching power, leakage mechanisms, IR drop, and timing/power interactions.

• Knowledge of V/F behavior, clocking, AVFS, voltage guardbands, and power-management architectures.

• Silicon Correlation & Variation Modeling

• Understanding of silicon variability (process variation, Vmin, FO2 timing spread, aging).

• Familiarity with statistical modeling, Monte Carlo analysis, or UPFM-like frameworks.

• Experience analyzing ring oscillator data, telemetry, or embedded monitors.

• Design, Firmware & Debug Knowledge

• Working knowledge of digital logic design, RTL fundamentals, and physical design constraints.

• Understanding of clock gating, power gating, voltage domains, and on-die regulation.

• Exposure to design-for-debug, PSS, or validation toolchains.

• Programming & Data Analysis

• Strong experience with Python (Num Py/Pandas/Scipy), Excel modeling, and scripting.

• Database experience (SQL, Parquet, analytics pipelines) is a plus.

• Ability to build reproducible modeling environments and automated analysis tools.

• Education Requirements

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, Applied Physics, or related field with 4+ years of relevant experience

• OR

• B.S. with 6+ years of industry experience in power modeling, silicon analysis, or performance engineering.

Ideal Candidate Profile The ideal candidate is:

• Strong in mathematical modeling, silicon physics, and systems thinking.
• Excited to work hands-on with both models and real silicon data.
• Able to operate across architecture, design, and product disciplines.
• Passionate about building frameworks that guide billion-dollar product decisions.
• Comfortable owning end-to-end solutions—from analysis → modeling → calibration → productization.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
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