포지션 소개
Job Description:
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Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies
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Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation
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Verify DFT circuitry and interface with other blocks, debug timing simulation issues
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Closely work with physical design team to resolve timing constraints/issues
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Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning
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Work independently and own the task from DFT specification to final pattern delivery
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Qualification
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BCH and above in EE, CS related fields.
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3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs
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Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST
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Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus
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Strong programming skills in Python/TCL and shell scripting is required
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Proficiency in English is a must"
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
TSMC 소개