포지션 소개
Job Description:
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Verify TSMC’s product like ARM processor based SOC and memory subsystem test chips
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Develop verification methodology and implement test bench components using System Verilog, UVM, and low power verification
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Develop comprehensive test plan and implement test cases to verify different test chips
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Work closely with Design and DFT teams to develop/verify various functional/DFT tests
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Write functional cover groups and cover points for coverage closure. Perform RTL code coverage, System Verilog Assertion coverage, System Verilog functional coverage
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Drive and adopt new verification methodologies and flows for efficiency improvements.
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Qualification
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BCH and above in EE, CS related fields with 3-15 years of hands-on experience
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Strong problem solving, debugging and programming skills (Python/TCL/C++)
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Strong hands-on experience with architecting and developing IP/SoC level reusable verification environments using System Verilog UVM methodologies.
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Hands-on experience developing testbench and testcases in System Verilog
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Knowledge in Constrained Random and Coverage Driven testbench
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Gate Level Simulation experience
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Proficiency in English is a must"
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
