Company:

Qualcomm India Private Limited:

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

We are looking for a highly experienced STA/Timing CAD Methodology Lead to own, architect, and scale the next generation of static timing analysis methodologies for cutting‑edge, high‑performance SoC designs. In this role, you will be the technical force behind enabling robust STA flows, accelerating ECO convergence, and shaping the timing closure strategy for complex designs in advanced technology nodes.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR
  Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  OR
  PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

What You Will Lead & Influence:

As the STA CAD Methodology Lead, you will:-Define, develop, and deploy industry‑leading STA and ECO methodologies across multiple design teams.

• Drive continuous innovation in timing flows, improving runtime, accuracy, and overall execution efficiency.
• Own end‑to‑end STA methodology, from constraints development to timing closure sign‑off.
• Collaborate closely with PNR, RTL, Extraction, and Technology teams to ensure smooth convergence at both block and top levels.
• Tackle complex timing challenges on advanced nodes to guarantee first‑time‑right tapeouts with exceptional quality.
• Guide and mentor a high‑performing STA CAD team, fostering a culture of excellence, ownership, and innovation.

Your Technical Expertise:

• We are looking for a leader with:-Deep knowledge of the ASIC design cycle, with strong expertise in timing closure flows and methodologies.
• 10+ years of hands-on experience in STA constraints, timing analysis, and closure.
• Expert-level proficiency in industry-standard STA tools such as Prime Time, Tempus, Tweaker, Prime Closure.
• Strong understanding of advanced STA concepts, OCV/POCV/AOCV, SI/IR implications, and timing bottlenecks at advanced nodes.
• Scripting mastery in TCL, Perl, Python, enabling robust automation and flow enhancements.
• Solid background in PNR, extraction, and timing-driven optimization.
• Experience with constraints verification tools (e.g., Fishtail(TCM)/Timevision) - a strong plus.
• Demonstrated technical leadership skills with the ability to influence, mentor, and lead a team.
• Experience with Multi-die, Die-to-Die interfaces, and 3DIC Signoff solutions preferred.
• Knowledge of Hierarchical Timing Signoff (Hyper Scale/Boundary model) solutions
  Qualifications-BE/BTech + 10 years of experience, or
• ME/MTech + 10 years of experience in VLSI, EDA, CAD, or related domains.

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