We are looking for an early‑career engineer to support AMS (Analog‑Mixed‑Signal) Digital Integration activities for next‑generation semiconductor designs.
This position provides hands‑on exposure to:

• Mixed‑signal IP integration
• Basic RTL coding and digital build flows
• AMS simulation environments
• Lab validation and measurements
• Cross‑functional collaboration (analog design, digital design, verification, CAD)
  You will work closely with experienced engineers who will mentor you in full‑chip integration,mixed‑signal verification, and silicon bring‑up—ideal preparation for an MSEE program or an early engineering career.

Key Responsibilities

Mixed‑Signal Integration (Entry-Level Scope)

• Assist in integrating analog and digital blocks into top‑level AMS environments.
• Prepare schematic and netlist views used for AMS simulations.
• Run automated connectivity and interface checks under supervision.
• Support mixed‑signal view generation (symbol, Verilog, Verilog‑AMS, wreal).

RTL Coding & Digital Support

• Write and modify simple RTL modules (wrappers, muxes, registers, glue logic).

• Assist with integration into digital‑on‑top flows:

• Linting

• Elaboration

• Basic synthesis checkpoints

• Create small testbench utilities to validate RTL functionality.

AMS Simulation & Verification Tasks

• Run AMS simulations (Spectre/Xcelium/AMS Designer) for block‑ and top‑level tests.
• Collect waveforms, create summary plots, and help analyze failures.
• Update or create simple AMS testbenches and configuration files.

Lab Validation & Silicon Bring‑Up (Hands-on)

• Support bench measurements for AMS blocks and subsystems:

• Oscilloscope measurements

• Power‑up sequences

• Data capture using automation scripts

• Reproduce issues seen in silicon or lab setups.

• Follow proper lab/equipment handling and safety procedures.

Tool Flow & Documentation

• Assist in model packaging, scripting, and build logistics.
• Update internal documentation, integration guides, and test logs.
• Participate in team meetings and cross‑discipline design reviews.

Minimum Qualifications (Post‑BSEE / BSECE or Pre‑MSEE)

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or closely related field.

• Solid academic grounding in:

• Analog circuits

• Digital logic design

• SPICE simulation

• HDL coding (Verilog preferred)

• Hands‑on experience through coursework or projects with:

• Oscilloscopes, logic analyzers, power supplies

• SPICE / Cadence / Mentor simulation environments

• Simple RTL coding and testbenches

• Comfort with Linux, scripting basics (Python, Bash, TCL).

• Strong communicator, organized, and eager to learn.

Preferred Qualifications

(Not required but highly beneficial)

• Completed senior‑level coursework or projects in:

• Data converters (ADC/DAC)

• PLLs or clocking circuits

• Mixed‑signal IC design

• Familiarity with Verilog‑AMS, System Verilog, or wreal modeling.

• Prior lab/Co‑op experience in semiconductor or embedded domains.

• Exposure to Git, revision control, and automation scripts.

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:

$64,480 to $107,500 annually

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.