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Senior Design Engineer (SoC RTL)

NXP Semiconductors

Senior Design Engineer (SoC RTL)

NXP Semiconductors

San Diego (Innovation Dr)

·

On-site

·

Full-time

·

1mo ago

Compensation

$166,200 - $228,500

Benefits & Perks

Flexible work schedule

Parental leave

Remote options

Health benefits

Design tool subscriptions

Creative environment

Parental Leave

Healthcare

Required Skills

Figma

Sketch

Adobe Creative Suite

Senior Design Engineer (SoC RTL)

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020

Business Line Description

We are part of ACE Engineering, a central design organization within NXP, Implementing designs for multiple business lines in Automotive, Internet of Things (IoT), Digital Networking

Job Summary:

  • Building Subsystems and/or SoC RTL integration for Internal or Vendor driven IPs like ARM Cores, DDR, PCIe, Ethernet, DSP/AIML cores, GPU, VPU, MIPI-CSI, USB, Display Controller
  • Write Micro-Architecture and detailed design specification in close collaboration with architecture, circuit designers, DFT/Physical Design/Verification engineers.
  • Provide high-quality RTL description, including assertions, for the design.
  • Perform all aspects of the SoC design flow from high level design to Synthesis.

Key Challenges:

  • The team works on Best in class Leading technologies designing chips for future Autonomous EVs or IoT Devices.
  • Being life-critical application, all engineers are trained on Functional Safety and Design Quality standards to ensure correct by construction architecture and designs.
  • Perform concept studies and provide direction in terms of performance, gate count and power for various digital designs.
  • Existing team is a mix of Design Architects, Domain experts and Tools/Flows/Methodology/Process champions
  • Right set of people who can own full chip from Definition to Production.
  • Team is groomed to demonstrate right set of values like Customer First, Ownership, Collaboration, Speed and Quality.
  • Great opportunities to innovate with supportive and encouraging environment, converting into Patents, Defensive Publications and Trade Secrets with generous rewards.

Cross functional aspects:

  • The team members own and gain expertise in their specific areas of assignment, while collaborating with Global stakeholders.
  • The role also involves contributing to improvements in Tools, Flows and Methodologies across global design community, interacting with global sites.
  • There are opportunities to work in wide range of domains and learning through cross-functional handoffs and interactions

Job Qualifications:

  • MS or PhD in Electrical/Electronic/ Computer Engineering
  • Requires 8+ years of experience in high performance digital logic designs and SoC Integration using ARM Cores, Bus Protocols and Interconnects
  • Must have expertise on RTL Sign off checks (LINT, CDC, RDC, LEC, UPF)
  • Experience with Synopsys VCS or Cadence RTL simulator, Design Complier (DC) or RTL Compiler (RC or Genus), Verdi Debugging tool
  • Preferred Expertise:
    Clock/Reset/Power Management Architecture would be a plus
    Logic Synthesis and Timing Closure, Netlist ECO would be a plus
    ISO26262 based functional safety relevant microcontroller architectures is a plus
  • Self-motivated with Excellent written and verbal communication skills
  • Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components
  • Should be a team player and willing to work with cross functional teams in issues resolution
  • Experience collaborating with international teams
  • Experience mentoring junior team members and overseeing their work

Job Location:

  • Austin, TX or San Diego, CA

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:

$166,200 to $228,500 annually

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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About NXP Semiconductors

NXP Semiconductors

NXP Semiconductors produces secure connectivity solutions for embedded applications.

10,001+

Employees

Eindhoven

Headquarters

Reviews

3.9

44 reviews

Work Life Balance

3.8

Compensation

3.9

Culture

4.1

Career

3.6

Management

3.8

73%

Recommend to a Friend

Pros

Competitive compensation and benefits

Good work-life balance and flexible environment

Interesting projects and challenges

Cons

Room for improvement in processes

Work-life balance varies by team

Internal communication could improve

Salary Ranges

267 data points

Junior/L3

L3

Junior/L3 · Data Scientist

0 reports

$114,000

total / year

Base

$99,000

Stock

-

Bonus

$15,000

$96,900

$131,100

Interview Experience

42 interviews

Difficulty

3.1

/ 5

Duration

14-28 weeks

Offer Rate

33%

Experience

Positive 69%

Neutral 13%

Negative 18%

Interview Process

1

Phone Screen

2

Technical Interview

3

Hiring Manager

4

Team Fit

Common Questions

Technical skills

Past experience

Team collaboration

Problem solving