NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

Join NVIDIA, where we push the boundaries of what's possible! As a DFT Implementation Engineer, you will be part of a team that is at the forefront of innovation in AI and accelerated computing. This role offers you the chance to contribute to groundbreaking projects while collaborating with some highly skilled professionals in the industry. Based in Bangalore, Karnataka, you will play a crucial role in ensuring the flawless execution of our dynamic projects. If you're ambitious and passionate about making an impact, this is the perfect opportunity for you!

What you’ll be doing:

• Implement and integrate scan insertion and scan compression at gate/RTL level.

• Support Scan ATPG, pattern validation, and silicon bring-up of scan-related DFT features.

• Perform gate-level verification, debug DFT/scan issues, and support ECOs.

• Develop and improve DFX/DFT methodologies for next-generation designs.

• Work closely with CAD and external CAD venders in developing next DFX architectures in nvidia chips

• Collaborate with design, verification, and physical design teams to ensure DFX readiness.

What we need to see:

• BSEE/MSEE or equivalent experience.

• 2+ years of experience in DFT/DFX implementation.

• Strong knowledge of ASIC design flow, static timing analysis, and ECO handling.

• Hands-on experience with gate-level simulation and verification.

• Solid understanding of Scan ATPG, scan compression, and memory test concepts.

• Familiarity with JTAG (IEEE 1149.1) and related DFT standards.

• Proficiency in HDL and scripting languages.

• Strong analytical, debugging, and communication skills.