채용
Required Skills
C++
Python
Computer Architecture
Performance Modeling
System on Chip Design
Overview:
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, One Drive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Compute Silicon and Manufacturing Organization (CSME) team is instrumental in defining and delivering operational measures of success for the Cobalt program through hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. CSME is at the forefront of innovation and application of AI to silicon development workflows. We are looking for senior engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Performance Architect to join the team.
- Responsibilities- Develop performance modeling methodologies by creating and owning System on Chip (SOC) / Intellectual Property (IP) cycle-accurate/approximate performance models and analysis tools in C++ and Python.
- Use workload information and working with Micro-architects and Register Transfer Level (RTL) team to identify performance bottlenecks. Collaborate across functionally to propose architectural/microarchitectural changes and provide the required quantitative justification.
- Leverage AI tools and infrastructure for comprehensive performance modeling, including coding, performance tuning, and analysis.
- Verify the correlation of the SOC performance models to the RTL implementation.
- Work closely with the product architecture System On Chip (SOC) architecture teams, IP architecture, to ensure our SOC and IPs enable performant, efficient, and industry-leading systems.
- Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
Qualifications Required/Minimum Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Qualifications:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Additional or Preferred Qualifications
- 3+ years of experience developing SOC or IP performance models and benchmarks from conception to microarchitecture specification.
- Deep understanding of computer architecture, System on Chip (SOC) and system-software architectures, and their performance tradeoffs.
- Significant understanding of input/output (I/O), memory subsystems, coherency flows, interconnect, Quality of Service (QoS) traffic.
- Knowledge of performance monitors and post-silicon SOC and performance tuning is a plus.
- Excellent communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
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Pros
Excellent compensation and benefits package
Four-day workweek with improved work-life balance
Supportive managers and teams
Cons
High-pressure environment causing anxiety
Unprofessional interview processes
Limited creative work opportunities
Salary Ranges
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$163,358
total / year
Base
$141,875
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Bonus
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$163,358
$163,358
Interview Experience
7 interviews
Difficulty
3.7
/ 5
Duration
14-28 weeks
Offer Rate
14%
Experience
Positive 14%
Neutral 29%
Negative 57%
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Technical Interview
5
Onsite/Virtual Interviews
6
Final Round
7
Offer
Common Questions
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Past Experience
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