Overview

We are looking for a Senior Design Verification Engineer to join Microsoft's Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team. This is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, One Drive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and deliver trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

Responsibilities

• Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components.
• Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
• Develop Verification IP (VIP) components to verify home grown designs.
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
• Define and implement functional coverage and drive coverage closure.
• Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive.
• Develop scripts for verification and validation infrastructure.

Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• 3+ years of pre-silicon System on Chip (SOC), chip level, subsystem or IP verification experience.
• 3+ years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/Open Verification Methodology (OVM), and coverage-based verification.
• 3+ years of experience in System Verilog, C/C++, and scripting languages such as Python, Ruby or Perl.
• Demonstrated experience on one or more of the following: Coherency, Caches, Fabrics, Double Data Rate (DDR) controllers, Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Advanced e Xtensible Interface(AXI)/Coherent Hub Interface(CHI) protocol bridges or other complex IP/blocks or subsystems.
• Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.
• Experience creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM), Formal Verification and/or C/C++.
• Experience in automating verification processes using Python or another scripting language.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.