ASIC Implementation Engineer, Static Verification

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.
ASIC Implementation Engineer, Static Verification Responsibilities
Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC
Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC
Perform RTL Lint and work with the Designers to create waivers
Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,)
Work closely with the Design Engineers, DV Engineers, and Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Currently has a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
6+ years of experience in static verification tools
Experience with Lint, Clock Domain and Reset Domain crossing

Experience with SOC CDC signoff:

Knowledge of SOC integration (clocking, reset, PLL, etc.)
Knowledge of front-end ASIC flows
Experience with RTL design using System Verilog or other HDL
Experience with communicating across functional internal teams and vendors

Preferred Qualifications:

Experience with Netlist-CDC Analysis and improving MTBF:

Experience with SOC Design Integration and Front-End Implementation
Scripting and programming experience using Perl/Python, TCL, and Make
Experience with developing structural rule based checks for RTL & Netlist
Experience with Design Compiler, Spyglass, Prime Time, Formality, or equivalent tools
Knowledge of Timing/physical libraries, SRAM Memories

About Meta

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For those who live in or expect to work from California if hired for this position, please click here for additional information.
United States of America: $146,000/year to $209,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Equal Employment Opportunity:

Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.
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