
Physical Design Engineer, Reality Labs Silicon
포지션 소개
Meta's Silicon Engineering team is building custom silicon to power the next generation of virtual and augmented reality products, including VR headsets and AR glasses. As a Physical Design Engineer, you will translate RTL designs into optimized silicon implementations, working across floorplanning, placement, clock tree synthesis, routing, and signoff to deliver high-performance, power-efficient chips. In this role, you will collaborate closely with architecture, design, and verification teams to shape the physical implementation strategy for wearable and spatial computing devices that define the future of human connection.
Physical Design Engineer, Reality Labs Silicon Responsibilities
Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification
Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products
Perform static timing analysis and timing closure across multiple process corners and operating conditions
Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off
Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions
Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements
Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes
Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization
Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency
Minimum Qualifications:
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience in physical design of complex digital ASICs or So Cs, including floorplanning, placement, CTS, routing, and sign-off
6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below)
Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent
Experience with physical verification flows including DRC, LVS, and antenna sign-off
Experience with power analysis and power delivery network implementation, including IR drop and electromigration analysis
Preferred Qualifications:
Experience with physical design implementation tools such as Synopsys Fusion Compiler (including Fusion Pilot/ConfigAI for run analysis and TCL configuration), Cadence Innovus, StarRC, and Prime Time
Experience with physical design for low-power wearable or mobile So Cs, including multi-voltage domain and power gating implementation
Experience developing and maintaining physical design automation scripts using Python or Tcl to improve implementation flows
Familiarity with co-design methodologies that bridge RTL microarchitecture decisions and physical implementation constraints
Experience with advanced node process design kits (5nm or below) and associated physical design challenges
About Meta
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and Whats App further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
For those who live in or expect to work from California if hired for this position, please click here for additional information.
United States of America: $146,000/year to $209,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity:
Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.
Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.
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필수 스킬
Semiconductor design
Validation
Technical documentation
