About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact
We are seeking a highly skilled and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team. The ideal candidate will have a deep understanding of the physical verification process in the context of semiconductor design and manufacturing. This role involves working closely with design and layout teams to ensure the integrity and performance of Marvell's advanced semiconductor products.

• What You Can Expect
• ​Develop run sets for nanotechnology and support Calibre, ICV and provide user support for DRC and LVS debugging to streamline physical verification flow. Automate and support physical verification flow for internal design tools group. Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration. Develop and maintain validation procedures for physical verification flow and prepare user guides and documents. Job duties include some usage of full custom layout tools to review results and create validation test cases.

• *CAD and EDA Tool Development: Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation.

• *Tool Integration: Integrate various EDA tools into an efficient and cohesive design flow, ensuring seamless interoperability and maximizing design productivity.

• *Methodology Development: Define and optimize design methodologies, flows, and best practices for efficient and reliable chip design, from  physical verification to SoC tapeout

• *Design Automation: Automate design tasks, including physical verification flow, design rule decks, automate layout migration, to improve design efficiency and reduce time-to-market.

• *Tool Evaluation and Selection: Evaluate and select third-party EDA tools, libraries, and IPs to meet project requirements, considering performance, scalability, and cost-effectiveness.

• *Collaboration and Support: Collaborate with cross-functional teams, including, foundry engineers, design engineers, layout designers, and software developers, to provide technical guidance, support, and training on CAD and EDA tools and methodologies.

• *Tool Performance and Maintenance: Monitor and optimize tool performance, addressing any issues or bottlenecks, and ensuring tool reliability, stability, and usability across design projects.

• I ndustry Awareness: Stay up-to-date with the latest advancements in CAD and EDA tools, methodologies, and industry trends, and provide recommendations on incorporating new technologies to enhance design capabilities.

• *Documentation and Training: Create and maintain comprehensive documentation, user guides, and training materials for CAD and EDA tools and methodologies, enabling efficient knowledge transfer and onboarding of new team members.

• What We're Looking For
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 6 years of experience.
• A minimum of 10 years of experience in CAD and EDA tool development and support, preferably within the semiconductor industry.
• CAD and EDA Expertise: In-depth knowledge and hands-on experience with industry-standard EDA tools and methodologies for digital and analog IC design, verification, and physical implementation. Proficiency with tools such as Cadence, Synopsys, Mentor Graphics, and scripting languages like Tcl, Perl, Python. Synopsys ICV is required, and Mentor Calibre svrf / tvf is preferred.
• Design Flow: Strong understanding of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation (place and route, timing analysis, physical verification).
• Problem-solving Skills: Demonstrated ability to analyze complex design and tool-related issues, propose innovative solutions, and drive them to completion.
• Team Collaboration: Excellent interpersonal and communication skills, with a collaborative mindset and the ability to work effectively with cross-functional teams.
• Leadership: Proven experience in leading projects or initiatives, providing technical guidance, and mentoring junior engineers.
• Continuous Learning: Strong motivation for staying abreast of the latest advancements in CAD and EDA tools and methodologies, and a passion for innovation and continuous improvement.

Expected Base Pay Range (USD)
124,420 - 186,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements:

At Marvell, we offer a total compensation package with a base, bonus and equity.

Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

_Interview Integrity__As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, Co Pilot, or note-taking bots) during interviews.__Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process._This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.