Job Details:

Job Description:

We are seeking an experienced Silicon Architect to lead the definition and architectural development of compute subsystems for next-generation ARM-based So Cs. This role focuses on high-performance compute cluster design, including ARM core complexes, CMN/CCN mesh interconnects, memory subsystem architecture, and system-level performance modelling. The ideal candidate will also bring strong expertise in networking architectures, packet-processing flows, and high-bandwidth data movement, enabling optimized silicon solutions for advanced networking and data-centric products.

Key Responsibilities

1. Lead the architectural definition of compute clusters for advanced ARM-based So Cs, including:

• CPU core complexes (Cortex-A, Neoverse).
• ARM CMN mesh and interconnect topology.
• Coherent and non-coherent system fabric integration.

1. Drive memory subsystem architecture, including:

• Memory controller definition (DDR, HBM, LPDDR)
• Cache hierarchy design and coherency strategy
• Traffic-flow analysis and performance bottleneck resolution

1. Develop and maintain high-level performance, power, and area (PPA) requirements to guide design tradeoffs and optimization.

2. Work with modelling teams throughout development lifecycle to correlate and drive architecture choices.

3. Work closely with cross-functional teams (RTL, verification, physical design, firmware, and software) to ensure architecture intent is maintained throughout implementation.

4. Evaluate and integrate IP blocks including accelerators, I/O subsystems, and security modules into a cohesive system architecture.

5. Provide architectural leadership for networking-centric flows with compute and memory, including:

• Packet-processing pipelines.
• QoS and traffic-management features.
• High-bandwidth and low-latency data-flow design.

1. Drive system-level interconnect requirements, bandwidth analysis, and thermal/power feasibility studies.

2. Author high-quality architecture specifications, performance projections, and design guidelines.

Qualifications:

Minimum Qualifications:

1. 4+ years of experience in SoC or CPU subsystem design, micro-arch or architecture, with experience in ARM-based designs.

2. Strong analytical skills with the ability to evaluate complex tradeoffs across performance, power, area, and cost.

3. Excellent written and verbal communication skills.

4. Experience in one of the following:

• ARM CMN/CCN interconnects.
• ARM cache-coherency protocols (CHI, ACE).
• Compute cluster microarchitecture and scaling methodologies.

Preferred Qualifications:

1. Experience with datacenter, telco, or edge networking silicon.

2. Proven experience defining or architecting memory subsystems (DRAM controllers, cache hierarchy, prefetching, coherency).

3. Solid understanding of networking architectures, including:

• L2-L4 networking flows.
• Traffic shaping, congestion control, packet processing.
• Data-path acceleration techniques.

1. Familiarity with process and manufacturing trade-offs as well as advanced packaging.

2. Experience in hardware-software co-design, firmware, and low-level drivers.

3. Background in large-scale SoC bring-up and silicon validation.

Job Type:

Experienced Hire

Shift:

Shift 1 (Ireland)

Primary Location:

Ireland, Leixlip

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.