招聘
Job Details:
Job Description:
Seize the opportunity to join the team behind the RTL logic design and development of chipsets that power PCs used by millions of people worldwide.
We're looking for an experienced, disciplined, and highly collaborative IP Logic Design Engineer to join our Chipsets Logic Team (CLIPS) in Singapore. If you're passionate about RTL design and want to work on industry leading client chipsets, this is your chance to make real impact at global scale.
As an IP Logic Design Engineer, you will:
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Design and develop logic, write RTL, and run formal verifications for IPs that power full-chip designs used across millions of devices.
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Contribute to architecture and microarchitecture definition for next generation blocks.
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Optimize RTL and logic to meet power, performance, area, and timing goals - ensuring high design integrity end to end.
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Review and strengthen verification plans, debug failing tests, and drive corrective actions to ensure feature level correctness.
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Support SoC customers to achieve seamless IP integration and verification.
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Ensure high quality IP to SoC handoff through strong quality assurance practices.
You'll be part of a high impact engineering team shaping the future of client chipsets while working in a collaborative and growth driven environment.
Qualifications:
Minimum Qualifications:
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Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, or a closely related semiconductor field.
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Proven track record in hardware development for semiconductor products, with demonstrated technical leadership in IP, subsystem, or SoC development.
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Strong ability to analyze and solve complex silicon design and verification challenges.
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Excellent communication skills for cross functional collaboration across architecture, design, physical implementation, and validation teams.
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High ethical standards and the ability to operate effectively in a fast paced, technically dynamic environment.
Minimum Technical Requirements:
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12+ years of hands on experience in pre-silicon verification or RTL logic design.
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Expertise with System Verilog, scripting languages (Python/Perl/Shell/etc), power-aware simulation flows (VCS/Synopsys tools), RTL model builds, and DFT/DFV methodologies.
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Experience developing test plans, coverage strategies, and validation content aligned to high level silicon or IP architecture specifications.
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Familiarity with VLSI design flows, including structural and physical design processes, as well as SIP/HIP interoperability.
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Strong background in power-aware design and verification in modern low power semiconductor products.
Preferred Technical Skillsets:
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Experience with industry standard semiconductor bus and interface protocols such as AMBA, MIPI, USB, and PCIe.
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Solid understanding of chipset or CPU level power behavior, including power estimation and low power design techniques widely used in semiconductor products.
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In-depth expertise with PCI Express, including PCS, FEC, LTSSM, and high-speed data path microarchitecture for advanced silicon generations.
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Deep knowledge of high-speed digital design, achieving timing closure at GHz frequencies using pipelining, retiming, and advanced microarchitectural techniques; experience with synthesis, STA constraints, and timing analysis in semiconductor flows.
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Experience implementing low power optimization techniques such as clock gating, power gating, and power domain design.
Job Type:
Experienced Hire
Shift:
Shift 1 (Singapore)
Primary Location:
Virtual Singapore
Additional Locations:
Business group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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About Intel

Intel
PublicIntel inside.
120,000+
Employees
Santa Clara
Headquarters
$200B
Valuation
Reviews
3.5
3 reviews
Work Life Balance
3.0
Compensation
3.0
Culture
2.5
Career
2.5
Management
2.0
25%
Recommend to a Friend
Pros
Offers internship opportunities
Interview opportunities available
Cons
Major job cuts and layoffs
Spam emails after rejection
Poor communication practices
Salary Ranges
6 data points
Senior/L5
Senior/L5 · Advanced Field Service Engineering Data Analyst
1 reports
$132,904
total / year
Base
$102,234
Stock
-
Bonus
-
$132,904
$132,904
Interview Experience
2 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
System Design
Past Experience
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