Job Details:

Job Description:

Come join Intel Memory team as a system memory validation engineer enabling new memory technologies on Intel Data Center and Client products. The team's charter expands from memory architecture pathfinding, development and spec definition to technology enablement, characterization, and validation across memory technologies (DDR, LPDDR, HBM, others) by collaborating with industry leaders and enablers. In this role, you'll be interacting and collaborating with Intel's SOC and platform validation teams as well as lead memory suppliers, customers, and industry partners to design, develop, align and qualify new memory technology solutions for Intel's Data Center and Client products.
Note: This role requires regular onsite presence to fulfill essential job responsibilities.

• Defines, develops, and performs functional validation for memory and integrated So Cs, focusing on validation of memory IP, its interaction with other IPs, and system level features involving the memory subsystem.

• Applies various hardware and software level tools and techniques to ensure validation coverage and that memory performance goals (POR speed) are met.

• Reviews proposed memory and SoC design changes to assess impact on validation plans, tasks, and timelines.

• Develops memory validation methodologies and test plans, executes memory validation plans, and collaborates with other engineers for design validation, troubleshooting, and failure analysis.

• Performs memory and silicon debug to identify root causes and resolves all functional failures for memory subsystem issues.

• Tests interactions between various SoC features using validation infrastructure.

• Develops post silicon validation infrastructure (e.g., performance and error monitors, behavioral checkers, features coverage, and telemetry) and test environment used in validation testing.

• Publishes Memory validation and FA reports summarizing all memory validation activities performed, reviews results, and communicates to relevant teams.

• Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product and JEDEC specifications.

• Develops content to validate memory products for compliance with industry standard memory protocols.

• Develops tools and strategies for debug of high-speed memory interfaces.

• Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure Memory and silicon readiness.

Qualifications:

Minimum Qualifications:

• EE (Electrical Engineering or Computer Science) BS or MS degree with minimum 3 years of industrial experience.

• Fluent in English.

• Motherboard (schematic and layout) and BIOS/FW knowledge.

• Self-motivated, work independently with strong teamwork spirit.

Preferred Qualifications:

• Basic memory knowledge including operation, architecture, key DRAM parameters associated with SoC and system interaction.

• Experience of memory system validation and failure analysis.

• Familiar with Intel collateral (PDG, EDS) and tools (ITP, Python SV).

• Experience to analyze system test log.

• Familiar with Signal integrity (Scope and LA) measurement and analysis.

Job Type:

Experienced Hire

Shift:

Shift 1 (Taiwan)

Primary Location:

Taiwan, Taipei

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.