Job Details:

Job Description:

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, FUSE and BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST, Fusing requirement).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
• Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in DFT, SOC design, or related semiconductor design areas.
• Proven expertise in DFT techniques, including scan insertion, BIST, boundary scan, JTAG, fault simulation, Fusing and ATPG.
• Advanced knowledge of DFT tools such as Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, or similar EDA tools.
• Proficiency in hardware description languages such as Verilog, VHDL, or System Verilog.
• In-depth experience with RTL design and verification processes and methodologies.
• Strong knowledge of semiconductor manufacturing processes and test flow. Expertise in leading and mentoring DFT engineering teams, with a focus on professional development and knowledge sharing.
• Excellent problem-solving skills with the ability to troubleshoot complex design and testability issues.
• Strong communication and interpersonal skills to effectively collaborate with cross-functional teams.
• Proven track record of driving process improvements and implementing efficient DFT solutions in large-scale projects.

Preferred Qualifications:

• Experience with advanced test techniques such as DFT for low-power and high-performance SOC designs
• Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others
• Knowledge of Python or other scripting languages for automation.
• Experience with failure analysis, yield improvement and test cost optimization methodologies
• Experience with SOC (System on Chip) or complex multi-chip designs
• Experience in managing complex, high-visibility projects and working with senior leadership

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.