Jobs
Job Details:
Job Description:
- Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs.
- Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models.
- Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results.
- Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals.
- Candidate will be joining an expanding high speed IO design team involved in design and development of next Gen memory interface PHY on cutting-edge process nodes.
- Responsibility will primarily include ownership of various task involves : circuit design, validation, layout review, mixed signal validation, behavioral modelling and reliability validation.
- Collaborate with cross-functional teams to define design specifications and requirements.
- Contribute to the continuous improvement of design methodologies and processes.
Qualifications:
Job Qualification :
- Candidate should possess 10+ year of experience with at least a master's degree in electrical engineering or equivalent or strong fundamentals of CMOS design, RC circuits, high speed circuit design concept are a must for this roleo Candidate should have expertise of designing high speed IO circuits (Ser Des, LPDDR, DDR, HBM) such as transmitter, receiver, clocking, PLL, DLL etc.
Added advantage :
- Experience working with Post-Si and SoC team to debug the issue on pre/post Silicon
- Experience with tools like Spectre, Prime Sim, HSPICE , Virtuoso, ADE and Custom Compiler or equivalent schematic layout editor tools, Knowledge of DRC, LVS, and post-layout extraction tools
- Experience with performing measurement, and correlating measurements to simulations
- Experience with modeling and simulation of high-speed interface interconnects/channel
- Excellent analytical and problem-solving skills
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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About Intel

Intel
PublicIntel inside.
120,000+
Employees
Santa Clara
Headquarters
$200B
Valuation
Reviews
3.5
3 reviews
Work Life Balance
3.0
Compensation
3.0
Culture
2.5
Career
2.5
Management
2.0
25%
Recommend to a Friend
Pros
Offers internship opportunities
Interview opportunities available
Cons
Major job cuts and layoffs
Spam emails after rejection
Poor communication practices
Salary Ranges
6 data points
Senior/L5
Senior/L5 · Advanced Field Service Engineering Data Analyst
1 reports
$132,904
total / year
Base
$102,234
Stock
-
Bonus
-
$132,904
$132,904
Interview Experience
2 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
Common Questions
Coding/Algorithm
Technical Knowledge
Behavioral/STAR
System Design
Past Experience
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