포지션 소개
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
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Proficient in Verilog coding and RTL design, data path designs,
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Knowledge of RTL checks ex- LINT, SDC, CDC
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Familiar with synthesis flow and timing constraints
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Experience in writing Verilog testbench and running simulations.
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Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
We’re doing work that matters. Help us solve what others can’t.
복지 및 혜택
•교육비 지원
•스톡옵션
•401k
•유급 휴가
필수 스킬
Verilog
RTL design
Lint
CDC
SDC
Synthesis
Simulation
